Without transistors? Fdsoi Technology Assist SOC refinement to 10nm!

For mobile products such as smartphones and tablets, the SoC (System on Chip) is their heart. Recently, the Italian-French semiconductor (ST) has begun to face 28nm process SOC production complete depletion type SOI (FULLYDEPLETEDSILICONONINSULATOR:FDSOI) technology. The micro-refinement technology that drives low cost and high performance of mobile products has a new choice.

If fully depleted SOI (FDSOI) technology is used, it is not necessary to make the transistor three-dimensional to continue to push the SOC micro-refinement to the 10nm process. As the original semiconductor manufacturing technology and design technology can be used, so without a lot of cost can continue to promote the micro-process (Figure 1). This will be a good choice for equipment vendors who want to continue to enjoy the benefits of SOC micro-refinement in the future. For the complete depletion-type soi and CMOS process comparisons, see: "Altera or the use of full depletion SOI for its FPGA products?" 】

Better cost and performance than FinFET

Fdsoi is a technique (Fig. 2) that uses a thin oxide film (buriedoxide:box) to separate the transistor's tube body (channel) from the SI substrate and to reduce the tube body to a few nm thick so that the channel is completely depleted. This is the same as the three-dimensional transistor (FINFET), which is three-dimensional, which can effectively restrain the short channel effect with the increase of the gate length and the leakage current.

Note 1 channel depletion refers to the state of becoming an electron and a void carrier that is essentially non-existent.

FinFET is not available and Fdsoi has the advantage of being able to maintain the structure of a planar transistor like the original Bulkcmos technology. Compared with FinFET, "the manufacturing process is reduced, the process cost is greatly reduced, and the design technology of Bulkcmos is directly followed" (Philippemagarshack, executive vice president of Design and service of Fdsoi Semiconductor).

Manufacturing Fdsoi need to be more expensive than the SI substrate soi substrate, so the manufacturing cost is similar to Bulkcmos. The ability to use the original design technique is the biggest difference from the FinFET that require drastic changes in design tools and circuit layouts. Because it can reduce the limitation of circuit design, the integration is easy to improve.

Figure 1:14nm Process still maintains planar transistor

The Italian-French semiconductor will use the FDSOI technology to extend the planar structure of the transistor to the 10nm process. 2014 will be mass production of 14nm technology, 2016 will be the production of 10nm technology. (pictured by "Nikkei Electronics" based on the Italian-French semiconductor materials)

Figure 2: Ability to accommodate low cost and high performance

Transistors using Fdsoi technology can follow many manufacturing processes and design techniques used in Bulkcmos technology (a). Performance beyond Bulkcmos, especially when driving low power (b). (pictured by "Nikkei Electronics" based on the Italian-French semiconductor materials)

In the performance of working speed and power consumption, the magarshack of the Italian-French semiconductor believes that "FDSOI has more advantages than FinFET". FinFET with the three-dimensional channel, parasitic capacitance increased, the working speed is easy to reduce, and fdsoi can avoid this problem. In addition, in addition to the gate electrode side, the ultra-thin box layer can be applied to the substrate dynamic bias voltage, so the threshold voltage control is good. This feature can be fully used in SOC for mobile products with low driving voltage and prone to threshold voltage deviation.

The control technology of establishing the thickness of tube body film

However, Fdsoi lags behind FinFET in the production time. Intel in the United States has adopted FinFET from 2012 in the 22nm process microprocessor, and foundry companies such as Taiwan's TSMC (TSMC) are also preparing to use FinFET in the 16~14nm process, which starts in 2014.

Fdsoi's original problem was that it was difficult to control the thickness of the tubes with only a few nm. Because the thickness of the tube is the parameter that determines the transistor characteristic such as the threshold voltage, the thickness is thinned out every time the technology is replaced. With the development of micro-refinement, technical difficulty is increased, it is difficult to further reduce the thinning.

The Italian-French semiconductor has solved this problem by cooperating with the French renowned soi substrate manufacturer Soitec Corporation, the French Research and Development agency CEA-LETI and the CMOS technology partner, IBM, etc.

First, it will be applied to smart phone SOC

Fdsoi technology will be first applied to the soc of smartphones and tablets. Swiss St-ericsson, a joint venture subsidiary of the Italian-French semiconductor, will use the Technology Note 2 in the 28nm process Soc to be launched within 2012 years.

Note 2 The technical details of the SOC have been announced on the "IEDM (internationalelectrondevicesmeeting) 2012" held in San Francisco, USA, December 2012 10 ~ 12th. See: "Altera or for its FPGA products using full depletion of SOI technology?" 】

In the future, the Italian-French semiconductor will adopt FDSOI technology in the company's SOC for digital cameras and gaming consoles, and provide manufacturing technology to US globalfoundries companies so that external equipment manufacturers and semiconductor manufacturers can adopt the technology. The GlobalFoundries company plans to "provide FDSOI technology for 28nm technology from 2013 7 to September" (the company's global sales and marketing executive Vice President Michaelnoonen).