FPGA UART TX,簡單的FPGA串口發送模組

串口資料大家網上找找,我也是個新手,歡迎交流.

//UART發送模組,傳輸速率9600//陳鵬//20120118 module UART_TX(sys_clk,//系統時鐘輸入reset_n,//非同步複位輸入Tx,//資料線TxData,//發送資料的資料線Tx_Start,//啟動發送訊號TX_STATE//發送器的狀態);inputsys_clk,reset_n,Tx_Start;input [7 : 0] TxData;outputTx,TX_STATE;reg Tx,TX_STATE;parameter SYS_CLK = 20000000;//系統時鐘parameter Tx_CLK = 9600;//9600bpsparameter TxDATA_W = 12;//傳輸速率時鐘發生器分頻寄存器位寬parameter TXCLK_DATA = SYS_CLK / Tx_CLK - 1;//傳輸速率分頻器時鐘分頻值//傳輸速率時鐘發生器reg[TxDATA_W-1 : 0] clk_cnt;regEN_TXCLK;//使能發送時鐘wireTX_CLK;//發送傳輸速率時鐘always @ (posedge sys_clk or negedge reset_n)if(!reset_n)clk_cnt <= 12'd0;else if(!EN_TXCLK)//不需要使能時鐘clk_cnt <= 12'd0;else if(clk_cnt == TXCLK_DATA)clk_cnt <= 12'd0;elseclk_cnt <= clk_cnt + 1'b1;assign TX_CLK = (clk_cnt == 0);//產生接收時鐘//發送控制狀態機器reg [3 : 0] TxState;reg [7 : 0] TxTemp;//存放需要發送的資料always @ (posedge sys_clk or negedge reset_n)if(!reset_n) beginTxState = 4'd0;TxTemp = 8'd0;TX_STATE = 1'b0;EN_TXCLK = 1'b0;endelse if ((TxState == 0) && (TX_STATE == 0) && Tx_Start) begin//匯流排空閑,並且有開始訊號,那麼開始發送資料EN_TXCLK <= 1'b1;//使能發送時鐘TxState <= 4'd1;//開始發送的第一個狀態TX_STATE <= 1'd1;//發送忙TxTemp <= TxData;//載入需要發送的資料endelse if(TX_CLK) begincase (TxState) //synthesis full_case4'd1:begin //發送起始位Tx <= 1'b0;TxState <= 4'd2;end4'd2:begin //發送bit0Tx <= TxTemp[0];TxState <= 4'd3;end4'd3:begin //發送bit1Tx <= TxTemp[1];TxState <= 4'd4;end4'd4:begin //發送bit2Tx <= TxTemp[2];TxState <= 4'd5;end4'd5:begin //發送bit3Tx <= TxTemp[3];TxState <= 4'd6;end4'd6:begin //發送bit4Tx <= TxTemp[4];TxState <= 4'd7;end4'd7:begin //發送bit5Tx <= TxTemp[5];TxState <= 4'd8;end4'd8:begin //發送bit6Tx <= TxTemp[6];TxState <= 4'd9;end4'd9:begin //發送bit7Tx <= TxTemp[7];TxState <= 4'd10;end4'd10:begin //發送同位位元,隨便發Tx <= 1'b0;TxState <= 4'd11;end4'd11:begin //發送停止位,高電平Tx <= 1'b1;TxState <= 4'd0;//進入空閑狀態EN_TXCLK <= 1'b0;//發送傳輸速率時鐘停在TX_STATE <= 1'd0;//發送邏輯空閑endendcaseend //end else ifendmodule