【筆記】5502 DSP reset序列（ Reset Sequence）

根據5502 Datasheet翻譯，原文見Datasheet 3.9.6節

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3.9.6  複位序列

當RESET#訊號為低（LOW）時，時鐘發生器進入旁路模式（bypass mode），此時根據GPIO4的狀態的不同，輸入時鐘被置為CLKIN或X2/CLKIN。當RESET#管腳的電平由低轉高時，以下事件將會按照下列順序依次進行。

• GPIO6和GPIO7在reset訊號的上升沿時刻被採樣。GPIO6和GPIO7的狀態決定了5502複用引腳的功能，（詳見5502 datasheet 3.3節，可配置的外部連接埠和訊號）。GPIO6和GPIO7的在reset上升沿時的狀態分別決定了外部匯流排控制寄存器（External Bus Control Register ，XBSR）中Parallel/Host Port Mux Mode bit以及Serial Port 2 Mux Mode bit的值。
• GPIO4在reset訊號的上升沿時刻被採樣，它的狀態將被用來設定始終模式控制寄存器（Clock Mode Control Register，CLKMD）的CLKMD0 位，該位用來決定DSP的時鐘源。CLKMD0位選擇內部振蕩器輸出（internal oscillator output ，OSCOUT）或X2/CLKIN管腳為DSP的輸入時鐘源。如果在reset時，GPIO4為低電平，則CLKMD0位被置為0，此時內部振蕩器和外部的晶體將為DSP產生輸入時鐘。如果在reset時，GPIO4為高電平，則CLKMD0位將被置為1，且輸入時鐘將直接由X2/CLKIN管腳提供。
• 當reset訊號由低變高時，DSP不會馬上從reset的狀態中結束。事實上，一個內部的計數器（internal counter）會計數41032個刻度來讓內部振蕩器狀態穩定（只在GPIO4位低電平狀態下發生）。另外，內部計數器還會增加70個參考刻度來讓reset訊號傳播到裝置的不同部分中。
• 當所有的內部延遲周期都完成後，BOOTM[2:0]管腳將被採樣，並且它們的值將被儲存在引導模式寄存器（Boot Mode Register，BOOTM_MODE）中。BOOTM_MODE寄存器中的值將被bootloader用來決定DSP的引導模式。
• 程式流將在所有的內部延遲周期結束後開始。

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3.9.6 Reset Sequence
When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or X2/CLKIN,
dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the following events
will occur in the order listed below.
• GPIO6 and GPIO7 are sampled on the rising edge of the reset signal. The state of GPIO6 and GPIO7
determines the function of the multiplexed pins of the 5502, see Section 3.3, Configurable External Ports
and Signals, for more information on pin multiplexing. The state of GPIO6 and GPIO7 during the rising
edge of reset determines the values for the Parallel/Host Port Mux Mode and the Serial Port 2 Mux Mode
bits, respectively, of the External Bus Control Register (XBSR).
• GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock
Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0
bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source
for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the
external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and
the input clock will be taken directly from the X2/CLKIN pin.
• After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately.
Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only
if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal
to propagate through different parts of the device.
• After all internal delay cycles have expired, the BOOTM[2:0] pins will be sampled and their values will be
stored in the Boot Mode Register (BOOTM_MODE). The value in the BOOTM_MODE register will be used
by the bootloader to determine the boot mode of the DSP.
• Program flow will commence after all internal delay cycles have expired.