標籤:初始化 建立 code 參考 輸入 amp ati address always
一:前言
這篇部落格是我應一位網友之約寫的,他想要學習基於FPGA的PCIe DMA控制器設計,但是手上沒有合適的Xilinx開發板,而且xapp1052又沒有提供模擬代碼,讓他的學習陷入了困境。所以我想了想,還是用EDK搭建一個微小系統,然後用modelsim來模擬xapp1052的DMA收發控制,這樣應該是最全面的理解PCIe_DMA了,希望對大家都有協助。
二:前期準備
1、Xapp1052 Demo(http://download.csdn.net/download/yuzeren48/7723795)
2、ISE14.1套件
3、基本會使用EDK(主要是Xilinx Platform Studio,XPS 和 Software Development Kit,SDK)
三:操作步驟
1、編譯庫檔案,將D:\Xilinx\14.1\ISE_DS\ISE\verilog\mti_se\10.1b\nt\modelsim.ini中選中部分複製粘貼到D:\modeltech_10.1b\modelsim.ini中
2、開啟XPS,建立一個最小系統,使用microblaze和PLB匯流排,匯流排上掛載的硬體IP2所示,硬體的匯流排地址3所示。
圖2 硬體IP
圖3 硬體IP匯流排地址
3、完成硬體系統搭建後,匯出到SDK
4、開啟SDK後,先建立一個BSP包,步驟請參考《Xilinx FPGA開發實用教程》
然後建立一個空的Xilinx C Project,命名為example。
在E:\xapp1052\dma_performance_demo\win32_sw\win32_driver\source下找到ioctrl.h,複製粘貼到E:\pcie_edk\EDK\workspace\example\src
在src中添加C檔案,命名為RC_example.c。再將
D:\Xilinx\14.1\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\pcie_v4_01_a\examples\xpcie_rc_enumerate_example.c中的代碼複製到RC_example.c中
對RC_example.c做如下修改:
//#define PCIE_CFG_BAR_0_ADDR 0x11110000#define PCIE_EP_CFG_BAR_0_ADDR 0x0000FFFF // Remote EP BAR0#define PCIE_RC_CFG_BAR_0_ADDR 0x0000EEEE // RC BAR0
添加:
//-------------------BMD Mrd Test*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + DCR_OFFSET) = Xil_EndianSwap32(0x00000001); //1. DMA assert reset*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + DCR_OFFSET) = Xil_EndianSwap32(0x00000000); //*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_ADDR_OFFSET) = PCIE_RC_CFG_BAR_0_ADDR; //2. Read DMA TLP Address Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_SIZE_OFFSET) = Xil_EndianSwap32(0x0000050/4); //3. Read DMA TLP Size Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_COUNT_OFFSET) = Xil_EndianSwap32(0x00000100); //4. Read DMA TLP Count Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_PATTERN_OFFSET) = Xil_EndianSwap32(0xA3A2A1A0); //5. Read DMA Data Pattern Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + DCSR_OFFSET) = Xil_EndianSwap32(0x00010000); //7. MWr start
或者
//-------------------BMD Mrd Test*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + DCR_OFFSET) = Xil_EndianSwap32(0x00000001); //1. DMA assert reset*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + DCR_OFFSET) = Xil_EndianSwap32(0x00000000); //*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_ADDR_OFFSET) = PCIE_RC_CFG_BAR_0_ADDR; //2. Read DMA TLP Address Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_SIZE_OFFSET) = Xil_EndianSwap32(0x0000050/4); //3. Read DMA TLP Size Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_COUNT_OFFSET) = Xil_EndianSwap32(0x00000100); //4. Read DMA TLP Count Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + READ_PATTERN_OFFSET) = Xil_EndianSwap32(0xA3A2A1A0); //5. Read DMA Data Pattern Register*(unsigned int*)(XPAR_PLBV46_PCIE_0_IPIFBAR_0 + DCSR_OFFSET) = Xil_EndianSwap32(0x00010000); //7. MWr start
在初始化RC端配置寄存器時,添加代碼:
//---------------------------------------------------- Configure RC//Write Address to PCIe BAR0HeaderData = PCIE_RC_CFG_BAR_0_ADDR;XPcie_WriteLocalConfigSpace(XlnxRootComplexPtr, PCIE_CFG_BAR_0_REG, HeaderData);
將RC端pcie_bar0設為0x0000EEEE (有大小端,故實際地址為0xEEEE0000)。
在枚舉使需要初始化遠端EP,修改代碼,使能master enable bit:
ConfigData |= (PCIE_CFG_CMD_BUSM_EN | PCIE_CFG_CMD_MEM_EN | 0x80000000 //master enable bit );
修改EP端pcie_bar0為0x0000FFFF(有大小端,故實際地址為0xFFFF0000):
/* Write Address to PCIe BAR0 */ConfigData = (PCIE_EP_CFG_BAR_0_ADDR | PCIeBusNum | PCIeDevNum | PCIeFunNum);
最後,去掉所有printf函數,列印太慢了,影響模擬。
編譯後產生elf檔案,開啟XPS,設定sim executable:
在Edit中設定preference
然後點擊Generate HDL Files,再Launch Simulator
在開啟的modelsim指令碼欄中輸入c;
完成RC編譯,再輸入s; 開始對RC端模擬。
5、若要模擬整個PCIE DMA,則需要修改..\EDK\simulation\behavioral檔案夾下的system_tb.v,在system_tb.v中加入EP端使用者邏輯,修改如下:
// START USER CODE (Do not remove this line) // User: Put your stimulus here. Code in this // section will not be overwritten. initial begin pcie_sysclk_p = 1‘b1; forever #(fpga_0_clk_1_sys_clk_p_pin_PERIOD) pcie_sysclk_p = ~pcie_sysclk_p; //100MHz end initial begin pcie_sysclk_n = 1‘b0; forever #(fpga_0_clk_1_sys_clk_p_pin_PERIOD) pcie_sysclk_n = ~pcie_sysclk_n; //100MHz endreg EP_pcie_sysclk_p;reg EP_pcie_sysclk_n; initial begin EP_pcie_sysclk_p = 1‘b1; forever #(4000) EP_pcie_sysclk_p = ~EP_pcie_sysclk_p; //125 MHz end initial begin EP_pcie_sysclk_n = 1‘b0; forever #(4000) EP_pcie_sysclk_n = ~EP_pcie_sysclk_n; //125 MHz endwire ep_pci_exp_txp;wire ep_pci_exp_txn; [email protected]* begin plbv46_pcie_0_RXP_pin = ep_pci_exp_txp; plbv46_pcie_0_RXN_pin = ep_pci_exp_txn; endxilinx_pcie_2_0_ep_v6 # ( .PL_FAST_TRAIN("TRUE"))EP ( // SYS Inteface .sys_clk_p(EP_pcie_sysclk_p), .sys_clk_n(EP_pcie_sysclk_n), .sys_reset(fpga_0_rst_1_sys_rst_pin),`ifdef ENABLE_LEDS // Misc signals .led_0(led_0), .led_1(led_1), .led_2(led_2),`endif // PCI-Express Interface .pci_exp_txn(ep_pci_exp_txn), .pci_exp_txp(ep_pci_exp_txp), .pci_exp_rxn(plbv46_pcie_0_TXN_pin), .pci_exp_rxp(plbv46_pcie_0_TXP_pin)); // END USER CODE (Do not remove this line)
為了模擬方便,修改system_tb.v後,在E:\pcie_edk\EDK\simulation下建立bmd_sim檔案夾,將behavioral檔案夾下的system_tb.v拷貝到bmd_sim檔案夾中,編寫simulate_mti.do檔案,將需要編譯的ep端檔案(主要包括pcie硬核和xapp1052DMA)寫成.f檔案。
vlog -work work +incdir+E:/pcie_edk/Coregen/EP_1_7/v6_pcie_v1_7/example_design +define+SIMULATION +define+PCIE2_0 $env(XILINX)/verilog/src/glbl.v -f ../bmd_sim/ep_v6.fvlog -work work ../bmd_sim/system_tb.v
PCIE_DMA執行個體二:xapp1052的EDK模擬