U-Boot原始碼閱讀筆記（一） —— 對start.S的分析

本文主要分析與U-Boot啟動過程相關的彙編代碼cpu/pxa/start.S，目標平台以PXA270為例。

• 系統啟動執行的第一條指令

/* armboot - Startup Code for XScale */

.globl _start

_start: b    reset    /*跳轉到reset標號執行*/

• 設定cpu為superviser模式

reset:

    mrs    r0,cpsr            /* 讀cpsr寄存器狀態 */

    bic    r0,r0,#0x1f       /* 位清除，清除0x1f對應的位 */

    orr    r0,r0,#0x13      /* 設定M=10011，superviser 模式 */

    msr    cpsr,r0           /* 寫cpsr寄存器 */


    bl    cpu_init_crit        /* 跳轉到cpu_init_crit執行系統的關鍵初始化 */

• 
  系統關鍵初始化

cpu_init_crit:

    /* mask all IRQs  */

    ldr    r0, IC_BASE    /* r0 <- Interrupt-Controller base address */

    mov    r1, #0x00

    str    r1, [r0, #ICMR_OFFSET]    /* ICMR寄存器清零，屏蔽所有的中斷 */


    /*

     * before relocating, we have to setup RAM timing

     * because memory timing is board-dependend, you will

     * find a lowlevel_init.S in your board directory.

     */

    bl    lowlevel_init    /* 跳轉到lowlevel_init執行SDRAM相關的初始化，參見對lowlevel_init.S的分析 */


#if defined(CFG_CPUSPEED)

/*

 * 系統頻率的計算方法如下：

 * Turbo-mode frequency (T) = 13-MHz processor-oscillator frequency * L * N

 * Run-mode frequency (R) = 13-MHz processor-oscillator frequency * L

 * System-bus frequency = 13-MHz processor-oscillator frequency * L / B,

 * where B = 1 (when in fast-bus mode) or B = 2 (when not in fast-bus mode)

 * For CCCR[A] = 0 :

 * Memory-controller frequency = 13-MHz processor-oscillator frequency * L / M,

 * where M = 1 (L = 2-10), M = 2 (L = 11-20), or M = 4 (L = 21-31)

 * LCD frequency = 13-MHz processor-oscillator frequency * L / K,

 * where K = 1 (L = 2-7), K = 2 (L = 8-16), or K = 4 (L = 17-31)

 * For CLKCFG[B] = 0 and CCCR[A] = 1 :

 * Memory-controller frequency = 13-MHz processor-oscillator frequency * L / 2

 * LCD frequency = 13-MHz processor-oscillator frequency * L / K,

 * where K = 1 (L = 2-7), K = 2 (L = 8-16), or K = 4 (L = 17-31)

 * For CLKCFG[B] = 1 and CCCR[A] = 1 :

 * Memory-controller frequency = 13-MHz processor-oscillator frequency * L

 * LCD frequency = 13-MHz processor-oscillator frequency * L / K,

 * where K = 1 (L = 2-7), K = 2 (L = 8-16), or K = 4 (L = 17-31)

 */

    /* set clock speed */

    ldr    r0, =CC_BASE

    ldr    r1, cpuspeed

    str    r1, [r0, #CCCR_OFFSET]    /* Core Clock Configuration Register */

    ldr    r1, [r0, #CCCR_OFFSET]        /* read back to make sure write action completed */


    mov    ip, lr    /* 臨時寄存器  <- 連結寄存器*/

    bl    xlli_freq_change    /* 跳到標號xlli_freq_change執行 */

    mov    lr, ip


/* Before enabling fast bus mode, must make sure Memory Controller is configured properly */

#if defined(CONFIG_SYSBUS_208)

    mov    r0, #0x0B        /*  Fast bus | Freq. Change | Turbo mode */

#else

    mov    r0, #0x03        /* ~Fast bus | Freq. Change | Turbo mode */

#endif

    mcr    p14, 0, r0, c6, c0, 0    /* Write CCLKCFG */


#if defined(CONFIG_MEMC_BS)    /* memory controller buffer strength control */

    ldr    r0, =MEMC_BASE


    ldr    r1, =CFG_BSCNTR0_VAL

    str     r1, [r0, #BSCNTR0_OFFSET]

    ldr    r1, =CFG_BSCNTR1_VAL

    str     r1, [r0, #BSCNTR1_OFFSET]

    ldr    r1, =CFG_BSCNTR2_VAL

    str     r1, [r0, #BSCNTR2_OFFSET]

    ldr    r1, =CFG_BSCNTR3_VAL

    str     r1, [r0, #BSCNTR3_OFFSET]


    ldr    r1, [r0, #BSCNTR3_OFFSET]    /* Make sure value is written */

#endif


setspeed_done:

#endif


.global normal_boot

normal_boot:


    /* Memory interfaces are working. Disable MMU and enable I-cache.   */


    ldr    r0, =0x2001        /* enable access to all coproc.        */

    mcr    p15, 0, r0, c15, c1, 0    /* enable access to CP13 CP0*/

    CPWAIT    /* wait for effect */


    mcr    p15, 0, r0, c7, c10, 4    /* drain the write & fill buffers   */

    CPWAIT


    mcr    p15, 0, r0, c7, c7, 0    /* flush Icache, Dcache and BTB        */

    CPWAIT


    mcr    p15, 0, r0, c8, c7, 0    /* flush instuction and data TLBs   */

    CPWAIT


    /* Enable the Icache                            */


    mrc    p15, 0, r0, c1, c0, 0

    orr    r0, r0, #0x1800    /* Instruction Cache Enable, Branch Target Buffer Enable */

    mcr    p15, 0, r0, c1, c0, 0

    CPWAIT


@    mov    pc, lr

    b    cpu_init_done        /* call return back */


/* Frequency Change Sequence from BLOB */

xlli_freq_change:

        mrc     p14, 0, r0, c6, c0, 0       /* Get present status (preserve Turbo and Fast Bus bits) */

        orr     r0,  r0,  #2                /* Set the F bit, Frequency Change, A change sequence is initiated when F is set. */

        mcr     p14, 0, r0, c6, c0, 0       /* initiate the frequency change sequence */

/*

 *      If the clock frequency is chaged, the MDREFR Register must be  rewritten, even

 *      if it's the same value. This will result in a refresh being performed and the

 *      refresh counter being reset to the reset interval. (Section 13.10.3, pg 13-17 of EAS)

 */

        ldr     r4,  =MEMC_BASE               /* Get memory controller base address */

        ldr     r1,  [r4, #MDREFR_OFFSET]      /* Get the current state of MDREFR */

        str     r1,  [r4, #MDREFR_OFFSET]      /* Re-write this value */


        mov     pc,  lr         /* return to calling routine */



    /* RS: ???                                */

    .macro CPWAIT    /* Canonical method to wait for CP15 update */

    mrc  p15,0,r0,c2,c0,0    /* arbitrary read of CP15 */

    mov  r0,r0        /* nop, wait for it */

    sub  pc,pc,#4    /* branch to next instruction */

    /* At this point, any previous CP15 writes are guaranteed to have taken effect. */

    .endm

• 系統初始化完成

cpu_init_done:


#ifndef CONFIG_SKIP_RELOCATE_UBOOT

relocate:                /* relocate U-Boot to RAM        */

    adr    r0, _start        /* r0 <- current position of code   */

    ldr    r1, _TEXT_BASE        /* test if we run from flash or RAM */

    cmp     r0, r1                  /* don't reloc during debug         */

    beq     stack_setup


    ldr    r2, _armboot_start

    ldr    r3, _bss_start

    sub    r2, r3, r2        /* r2 <- size of armboot            */

    add    r2, r0, r2        /* r2 <- source end address         */


copy_loop:

    ldmia    r0!, {r3-r10}        /* copy from source address [r0]    */

    stmia    r1!, {r3-r10}        /* copy to   target address [r1]    */

    cmp    r0, r2            /* until source end addreee [r2]    */

    ble    copy_loop

#endif    /* CONFIG_SKIP_RELOCATE_UBOOT */


    /* Set up the stack                            */

stack_setup:

    ldr    r0, _TEXT_BASE        /* upper 128 KiB: relocated uboot   */

    sub    r0, r0, #CFG_MALLOC_LEN    /* malloc area                      */

    sub    r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */

#ifdef CONFIG_USE_IRQ

    sub    r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)

#endif

    sub    sp, r0, #12        /* leave 3 words for abort-stack ,  sp　—— 棧指標寄存器   */


clear_bss:

    ldr    r0, _bss_start        /* find start of bss segment        */

    ldr    r1, _bss_end        /* stop here                        */

    mov     r2, #0x00000000        /* clear                            */


clbss_l:str    r2, [r0]        /* clear loop...                    */

    add    r0, r0, #4

    cmp    r0, r1

    ble    clbss_l

• 跳轉到start_armboot執行
  

    ldr    pc, _start_armboot    /* 跳轉到start_armboot執行，　參見對lib_arm/board.c的分析　*/


_start_armboot: .word start_armboot