fpga nes

I. SummaryThe FPGA implementation of the algorithm is combined with dsp_builder, Matlab, Modelsim and Quartus II software.Second, the experimental platformHardware platform: Diy_de2Software platform: quartus ii9.0 + modelsim-altera 6.4a (quartus II 9.0) + dsp_builder9.0 + matlab2010bIii. preparation of the software platform 1, software matchingBased on Altera's official documentation, you can see version matching information for Quartus II, Modelsim,

Last but not least, the structure of convolution neural network is built on FPGA. The FPGA I use is Xilinx's xc6slx45, and the following is the final resource usage One of the most important design is to solve the problem of two-dimensional convolution, I used the shift RAM IP core But there's a problem with using it: you need to get rid of some invalid data. Specifically as follows:

The three-state gate refers to the gate circuit output has 3 kinds of states: high level, low power and high impedance state. A three-state gate is required when more than two devices are used to drive the same signal line.At any one time, there can only be one device drive signal, other devices need to be set to high impedance state.Otherwise, if two devices drive the same signal at the same time, a device output high level, a device output low, for push-pull output, two devices equivalent to t

Label:Article source http://blog.chinaaet.com/detail/34609 Familiar with XPS operation, IP Add, bus connection Setup, graphical method check (open graphical Design view), check bus and port connection. In the icon below file, open Export to SDK and start, complete program writing. Refer to the superb sunny blog http://www.cnblogs.com/surpassal/, using XPS to add additional IPs to the PS processing system. Add a gpio from the IP Catalog tag and connect to the 8 LEDs on the Zedboard board. Wh

Altera's-6,-7,-8 speed level reverse order, Xilinx speed grade forward sort.Not very strictly, "the lower the number, the higher the speed level" This is the Altera FPGA sorting method,"The higher the serial number, the higher the speed level" is the Xilinx FPGA sorting method.Since then, I have not been able to understand how the speed grade, the only concept is: the same chip can have multiple speeds, dif

1 Introduction DDR2 (double data rate2) SDRAM is a new generation memory technical standard developed by JEDEC (Joint Committee for electronic equipment engineering). It is the biggest difference from the previous generation of DDR memory technical standards: although the basic method of transmitting data at the same time with the clock rising/falling edge, DDR2 has twice the DDR pre-read capability (that is, 4-bit pre-Access Technology ). In addition, DDR2 also adds the ODT (with built-in cor

ArticleDirectory Fault 1 Summary Introduction Whether it is customer feedback or your own experience, USB-blaster cannot download and configure FPGA from time to time. The reasons are as follows: 1. The JTAG-related pins on FPGA Devices are faulty; 2. the USB-blaster is broken; 3. The 10-pin JTAG cable is not properly pressed. Among them, Article 1 has brought the most serious damag

Abstract: The state machine frequently used in FPGA/CPLD design often has some stability problems. Some solutions are proposed in this paper. Experiments show that this method effectively improves the overall efficiency. With the emergence and development of large-scale and ultra-large FPGA/CPLD devices, the application of EDA technology, which uses HDL (hardware description language) as a tool and

Novice FPGA, a fall into your wit process.The FPGA Development board used the black Gold Learning Board ALINX301,FPGA model Cycloneiv ep4ce6f17c8n.Beginners, all from the light of the first LED light start.Module fisrtled (LED);Output [3:0] LEDs;Assign led=4 ' b1010;EndmoduleFound that the difference is that the 51 single-chip microcomputer used by the current-dr

Link: http://blog.ednchina.com/riple/41367/message.aspx I. Introduction to problematic asynchronous InterfacesRiple It is the sequence diagram of accessing the IDE Hard Drive Device by using MDMA on the host (PC). FPGA is used to design the interface on the device.Riple The Dior-/diow-signal is driven by the host. The rising edge of the "read/write" data on the "Dior-/diow-" signal is sampled by "host/

Crazy Bingolearn to walk first before your want to run ... Discussion on the factors affecting the clock in FPGA designHttp://www.fpga.com.cn/advance/skill/speed.htmHttp://www.fpga.com.cn/advance/skill/design_skill3.htmThe clock is the most important and special signal of the whole circuit, the movement of most of the devices in the system is on the hopping edge of the clock, which requires the clock signal PMD to be very small, otherwise it may cause

Design of serial communication system between FPGA and GPS-OEM Board [Date:] Source: Electronic Components application Author: Chen shilei, Liu Guixi, to Guohua [Font:Large Medium Small] 　 0 Introduction Global Positioning System (GPS) is the second generation of satellite navigation system in the United States. It is developed on the basis of the satellite navigation system of the Meridian Instrument. GPS can provide all-weather

FPGA-based FFT Processor Design [Date: 2008-10-23] Source: foreign electronic components by Yang Xing, Xie Zhiyuan, and Rong Li [Font:Large Medium Small] 　 1 IntroductionWith the rapid development of digital technology, digital signal processing has penetrated into various disciplines. In digital signal processing, many algorithms, such as correlation, filtering, spectral estimation, and convolution, can be implemented by converti

) light the first led and delay for a period of time. 2) light the second led and delay for a period of time. 3) light the third led and delay for a period of time. 4) light the fourth led and delay for a period of time. 5) Repeat the first step. From the above point of view, we understand that "the generation of the effect of the water lamp" mainly follows five steps in order. This may be a natural way of thinking. Humans are really strange animals. Although human brains operate in pa

Xilinx FPGA learning notes 1-chipscope cannot observe the signal BUFG, xilinx-chipscope Today, I started to try to use chipscope and wrote a simple routine of the Water lamp. There was no problem when I started the Integrated Wiring. However, after chipscope was added, an error was always reported. First case: Using chipscope cannot directly observe the global clock signal, that is, the BUFG signal ----- X The error is as follows: ERROR: Location: 113

Tags: FPGAIn some FPGAs, floating point numbers cannot be operated directly, but only fixed points can be used for numerical operations. For FPGA, the book involved in mathematical operations is a 16-bit integer number. What if there is a decimal number in the mathematical operation? You must know that FPGA is powerless to decimal places. One solution is to adopt calibration. The number calibration is to in

Debug fiber Interface interface with FPGA:Due to the needs of the project, the previous period of time debugging the optical fiber interface, recording some design experience.In the design, FPGA is used to control optical fiber module to complete the transmission of optical fiber data, FPGA uses Xilinx company's Spartan6 lx45t, because of its internal 2 GTP transceiver, can be used as a variety of communica