modelsim software

is in the process of learning SV, run the book on the examples, encountered problems. function: The function returns an array. Code1:/ * Examples provided in the book, there are errors, not runningfunction void init (ref int f[5], int start);//main function definition without declaring automatic propertyforeach (f)F= i + start;EndfunctionInitial beginint fa[5];FA = init (fa,5);foreach (FA)$display ("fa[%0d] =%0d", I, FA);End*/#---------------------------------------------------------------------

The author's computer was installed as a win8 system, and then opened Modelsim as usual, then jumped out of the interface:The author's Modelsim before is installed, so this interface has been explained that the current license is not installed. The solution to this problem is to reinstall the license.First copy the following two files to the Modelsim-->win64 fold

The computer has done the simulation before, Modelsim can be perfect to call, but recently inexplicably there is a flashback problem, not through the Quartus or Ise call, when used alone will also flash back.Occasionally, you can catch an error message. As shown in the following:But the egg, there is no solution on the Internet, the most is the proposed re-installation system. Fortunately, colleagues have a great God, lest I delay time, at the same ti

;Parameter N = 50;reg [7:0] mem[0:n-1];InitialBegin$READMEMH ("Sindata.txt", mem);Endreg [7:0] sin_out_buff;reg [5:0] I;[Email protected] (Posedge CLK or Negedge rst_n)Beginif (!rst_n)Beginsin_out_buffIEndElseBeginsin_out_buffif (i==6 ' D49)IElseIEndEndAssign Sin_out=sin_out_buff;Endmodule6, Testbench' Timescale 1ns/1psModule Testbench ();Reg Clk,rst_n;InitialBeginclk=0;Forever #10 CLK=~CLK;EndInitialBeginrst_n=0;#50 Rst_n=1 ' B1;EndWire [7:0] sin_out;Sin_gen U0_sin_gen (. CLK (CLK),. Rst_n (Rst

References: Http://hi.baidu.com/282280072/blog/item/ff8d88c36502302de4dd3b3c.html It took me several days to finally solve the problem of us II timing simulation. During simulation, there is always a strange error. vsim -voptargs=+acc work_test.tb# vsim -voptargs=+acc work_test.tb # Loading work_test.tb# Loading work_test.test# Loading work_test.cycloneii_io# Loading work_test.cycloneii_mux21# Loading work_test.cycloneii_dffe# Loading work_test.cycloneii_asynch_io# Loading work_test.cycloneii_

When I used Modelsim to simulate Rom last night, all the output data was 000. This was never done before. Is Modelsim broken?I tried a previous Rom test file and showed it to be normal. That's strange. Isn't it so unfamiliar if I haven't touched it for two months?Then start to find the cause. the Last Post says that if the Rom has no output, it may be the IP Core configuration file, and the absolute path mu

primary device sink (master Sink) and the output interface is the primary device source (master source).After the reset signal is invalid, the data source will be sink_valide to high efficiency, to the FFT notification at the input of at least N complex data sample points can be entered. FFT functions set the sink_ready signal high to indicate the ability to receive these input signals. When the Sink_ready (FFT core emitted) and the sink_valide are active simultaneously, the transmission begins

Open modelsimSE-64 10.1cCreate a new project corresponding to the location of the project name and other basic operationsBuild a Verilog file, which is the object of the simulation, File>source>verilog.Build a simulation file, that is, ***.TB, the method is also built a verilog empty file, click on the menu bar Source>show language templates. That is, templates.Click on the left Testbech to select the simulation target file next> finish. Adding the appropriate incentive in the new makefile is ge

File Operations are inevitable in ModelSim. Check the code operations in the window. Below is a piece of test code in my own M sequence experiment. 1 integer I, J, K, M; 2 3 integer m_datafile, 4 indatafile, 5 oudatafile; 6 7 Reg [] I _data [0: 9999]; 8 9 10 initial 11 begin 12 m_datafile = $ fopen (". /m_data.dat "); // M sequence storage file 13 indatafile = $ fopen (". /indata. dat "); // random number (data used for sending) storage file 14 oudat

ModelSim code coverage function code coverage, which can report statement, branch, condition, expression, and toggle) and FSM (finite state machine.1. Compile option ): In The Modelsim workspace, select the file for viewing code coverage, and right-click compile-> compile properties, as shown in. Select the "coverage" option. In the displayed window, select the options as needed. Here, select statement, b

Matlab to the Modelsim simulation data processing is also through the file read and write implementation. That is, through the Verilog statement, a signal in the simulation process is written to the file, and then in MATLAB in the data of this file read out, you can be analyzed in MATLAB.A simple example is also given to illustrate the whole process.The following Verilog statement is implemented to write the data of the signal data_out to the Data_out