#1 Power: counter. Trigger ......

22:39:30

#1 Power: counter... trigger ......

In addition to the counting function, the counter product also has some additional functions, such as Asynchronous Reset and preset quantity (Note: there are two types of synchronous preset quantity and asynchronous preset quantity. The former is controlled by the clock pulse, the latter is not controlled by the clock pulse), and (note, there are two types of hold carry and not hold carry ). Although there are only binary and decimal counter products, with these additional features, we can easily use the counters we can get to form any hexadecimal counter. Here are two examples. In these two examples, we use the synchronous decimal addition counter 74ls160 to form a hexadecimal counter and a one hundred hexadecimal counter. Because there are six valid states for the six-digit counter and ten valid states for the decimal counter, when the decimal counter is used to form the six-digit counter, we only need to keep the six statuses of the decimal counter. The ten valid states of 74ls160 are BCD encoded, that is, 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000 [Figure 5-1]. Figure 5-1 what six States do we keep? In theory, we can retain any six states. However, in order to make the circuit the simplest, it is still a little bit worth noting which six states are retained. Generally, we keep the 0000 and 1001 statuses. Because 74ls160 changes from 1001 to 0000, a carry pulse will be generated at the input output end, so after we keep the 0000 and 1001 statuses, we can use the carry output end of 74ls160 as the carry output end of the hexadecimal counter. As a result, the status cycles of the hexadecimal counter can be 0000, 0001, 0010, 0011, 0100, or 1001, or 0000, 0101, 0110, 0111, or 1000. We may wish to adopt the six States: 0000, 0001, 0010, 0011, and 0100. How can I redirect 74ls160 from 0100 to 1001? We use a mixed logic and a non-gate to form a decoder [figure 5.3.37b]. When the status of 74ls160 is 0100, it is low with the non-gate output. This low level enables 74ls160 to work in the preset status, when the next clock pulse arrives, 74ls160 is preset to 1001 because it is equal to 1001, so that we can skip the status. Figure 5.3.37b uses the set number method to connect 74160 to a hexadecimal counter (with 1001 in place). What is a little more complicated than this method is to use the Asynchronous Reset end of 74ls160. In the following circuit [figure 5.3.34], there is also a decoder consisting of a hybrid logic and a non-gate. Figure 5.3.34 uses the zero-setting method to connect 74ls160 to a hexadecimal counter. However, this decoder outputs a low level when the input is 0110, enabling the Asynchronous Reset of 74ls160 to enter the 0000 status. Starting from the 0000 status, the 74ls160 status changes to 0001, 0010, 0011, 0100, 0101, and 0110 as the clock pulse continues. [Figure 5-2]. Someone may say, "No! This circuit has a total of seven States. It should be a 7-in-one counter !" Although this circuit has to go through seven states, it only needs six pulses to complete a counting cycle, so it is still a hexadecimal counter. Figure 5-2 Let's analyze it carefully. Assume that the initial status of 74ls160 is 0000. After the first clock pulse arrives, its status changes to 0001. After the second clock pulse arrives, its status changes to 0010 ,......, When the fifth Clock Pulse arrives, its status changes to 0101. When the sixth Clock Pulse arrives, its status changes to 0110. When 74ls160 is in the 0110 status, the decoder outputs a low level, enabling 74ls160 to be asynchronously reset to the 0000 status. In this section, "Asynchronous Reset" is a keyword. Unlike Synchronous Reset, Asynchronous Reset is not controlled by the clock pulse. As a result, the output of the decoder is changed to a low level, and the 74ls160 status is changed to 0000. Ideally, 74ls160 stays in the 0110 status for a moment in the sixth clock cycle, and then steadily stays in the 0000 status. We know that the counter is working on a clock pulse. Counting refers to the number of clock pulses. In our example, 74ls160 starts from the 0000 status and goes back to the 0000 status after six (instead of seven) clock cycles, that is, every six (instead of seven) the Clock Pulse repeats the status of 74ls160 once. Therefore, this circuit is a hexadecimal counter. The counting cycle contains the six stable states: 0000, 0001, 0010, 0011, and 0100. Someone may say, "Well, I think it's a hexadecimal counter. However, it is always awkward to convert the seven States into six. Alas, as long as it can work, I don't care whether it goes through six states or seven states ." I said, "Yes, I think so too. However, this is counterproductive! This circuit cannot work without improvement ." Why? We know that the counter status is remembered by the trigger. 74ls160 has four triggers for memory respectively. The speed of these four triggers varies. In the process where 74ls160 is changed from 0110 to 0000, the sum State remains the same, and the sum state changes from 1 to 0. We assume that it is faster, so when we change from 1 to 0, it is still in the 1 state. In this case, the output of the decoder is not low, and the Asynchronous Reset signal of 74ls160 disappears. When the Asynchronous Reset signal lasts too short, it will remain in the 1 state. So 74ls160 will stay in the 0010 status, rather than the expected 0000 status. Obviously, this is a kind of Competitive Adventure, because whether 74ls160 can change from 0110 to 0000 depends on the competition results. How can the Asynchronous Reset signal be sustained for a long enough time? Let's take a look at this circuit [figure 5.3.36]. Figure 5.3.36 figure 5.3.34 circuit improvement two and non-gate constitute the RS latch, with its end output low level as 74ls160 Asynchronous Reset signal. If 74ls160 starts counting from the 0000 status, the sixth rising edge of the clock pulse enters the 0110 status when it reaches, so that the RS lock is set to a bit, and the end outputs a low level. After the 74ls160 remains in the 0110 status for a short time, it is quickly transferred to another status, such as 0010 or 0100. The negative pulse output by the decoder disappears. If we use this narrow pulse directly as the Asynchronous Reset signal of 74ls160, the counter may not work reliably. If we use this narrow pulse as the position signal of the RS lock, use the clock pulse as the reset signal of the RS lock, and then use the RS lock as the Asynchronous Reset signal of 74ls160, the counter must work reliably because the width of the output negative pulse is equal to the duration of the High-level clock pulse. The second example requires that we construct a one hundred hexadecimal counter, that is, the counter status is 0010 to 9910. Because 100 equals 10 multiplied by 10, we can use two 74ls160 to form a one hundred hexadecimal counter. The status of one counter indicates a single digit, and the status of the other counter indicates ten digits, the latter is counted under the carry signal control of the former. We have two solutions. The first scheme is called Parallel carry mode [figure 5.3.39]. Figure 5.3.39 example 5.3.3 the parallel carry mode of the circuit. This scheme features that both the CP ends of 74ls160 are connected to the clock pulse. However, the first 74ls160 always works in the counting mode, and every clock pulse changes its status. The first 74ls160 only works in the counting mode when the first 74ls160 carry output is high, the status of each 10 clock pulses changes. If the counter starts counting from the 0010 status, after the ninth Clock Pulse arrives, the status of the first 74ls160 changes to 910 and the carry output changes to a high level, so that the second 74ls160 enters the counting mode. Because the time when the second 74ls160 enters the counting mode is later than the time when the ninth Clock Pulse arrives, that is, when the ninth Clock Pulse arrives, the second 74ls160 has not yet entered the counting mode, the ninth Clock Pulse cannot change the status of the second 74ls160, but its status is still 010. The status of the counter is 0910. After the tenth Clock Pulse arrives, the status of the first 74ls160 changes to 010 and the carry output changes to a low level, so that the second 74ls160 exits the counting mode. Because the second 74ls160 exit counting method is later than the arrival time of the tenth clock pulse, that is, the second 74ls160 has not exited counting method when the tenth Clock Pulse arrives, so, the tenth Clock Pulse changes the status of the second 74ls160 to 110. The status of the counter is 1010. The second scheme is called the serial carry mode, which features that both 74ls160 always work in the counting mode. However, the CP End of the first 74ls160 is connected to the clock pulse, and the status of each Clock Pulse changes. The CP End of the first 74ls160 is connected to the first 74ls160 carry output, the status of each 10 clock pulses changes. Some students often ask: "Why should a non-door be added between the carry output end of the first 74ls160 and the clock pulse input end of the second 74ls160 ?" This is a bit mysterious. If the counter starts counting from the 0010 status, after the ninth Clock Pulse arrives, the status of the first 74ls160 changes to 910 and the carry output changes to a high level. Without this non-gate, the level change at the carry output end of the first 74ls160 changes the state of the second 74ls160, and the state changes to 110. Therefore, the status of the counter changes from 0810 to 1910, rather than the expected 0910. With this non-gate, the situation is different, because the rising edge of the first round output of 74ls160 is converted into a falling edge by the non-gate, therefore, the level change at the output end of the first 74ls160 does not change the status of the second 74ls160. The status is still 010. Therefore, the status of the counter changes from 0810 to the expected 0910. After the tenth Clock Pulse arrives, the status of the first 74ls160 changes to 010 and the carry output changes to a low level. Because the falling pulse of the first 74ls160 carry output end is converted into a rising edge by a non-gate switch, the level change of the first 74ls160 carry output end changes the state of the second 74ls160, the status changes to 110. Then the status of the counter changes from 0910 to 1010. Here is another example of using 74ls160 to construct a binary counter. 29 is a prime number. Apart from 1 and itself, it cannot be expressed as the product of two integers. Therefore, we need to break down the work into two steps. In the first step, we use two decimal counters to form a one hundred hexadecimal counter. In the second step, we use this one hundred hexadecimal counter to form a hexadecimal counter. The first step can be implemented using the parallel carry mode or serial carry mode; the second step can be implemented using the placement method or reset method. Because both 74ls160 are set or reset at the same time, it is also called the overall position method or the overall reset method.