28335scififo interrupt Receive and send

#include "dsp28x_project.h"//Device Headerfile and Examples include File

interrupt void Scibtxfifoisr (void);//fifo Send Interrupt function

interrupt void Scibrxfifoisr (void);//fifo receive interrupt function

void Scib_fifo_init (void);//SCIB FIFO mode initialization function

char buffer [100];//data buffer array

void Main (void)

{

Uint16 i;

Initsysctrl ();//System clock initialization

Initscigpio ();//sci Port Initialization

DINT; Turn off the interrupt

Initpiectrl (); PIE Module Initialization

IER = 0x0000;//Off CPU Interrupt

IFR = 0x0000;//Clear CPU Interrupt flag

Initpievecttable ();//Initialize the interrupt vector table, which can be commented out by testing this sentence, because the interrupt vector table is re-assigned below

Eallow; This is needed to write to Eallow protected registers

PIEVECTTABLE.SCIRXINTC = &scibRxFifoIsr; Interrupt vector Table re-assignment (the entry address of the custom interrupt function)

PIEVECTTABLE.SCITXINTC = &scibTxFifoIsr; Interrupt vector table re-assignment

EDIS; This is needed to disable write to Eallow protected registers

Scib_fifo_init (); Initializing the Sci-b register configuration

for (i = 0; i<100; i++)//cache initialization

{

Buffer[i] = 0;

}//Enable interrupts required for this. Example interrupt enable

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; Enable the PIE block

Piectrlregs.pieier8.bit.intx6=1; PIE Group 9, INT3 scirxintb SCIB

Piectrlregs.pieier8.bit.intx5=1; PIE Group 9, INT4 scitxintb SCIB

IER |= m_int8; Enable CPU INT

eint;//Open Total Interrupt Intm//Step 6. IDLE Loop. Just sit and loop forever (optional):

for (;;);

}

interrupt void Scibtxfifoisr (void)//fifo send interrupt Service subroutine

{

Uint16 i;

for (i=0;i<8; i++)

{

Scicregs.scitxbuf=buffer[i]; Send data sends out the cache

}//scibregs.scifftx.bit.txffintclr=1; If the interrupt flag is sent in the send interrupt, it will continue to be sent

PIECTRLREGS.PIEACK.ALL|=PIEACK_GROUP8;; Issue PIE ACK

}

interrupt void Scibrxfifoisr (void)//fifo receive interrupt Service subroutine

{

Uint16 i;

for (i=0; i<8; i++)

{

Buffer[i]=scicregs.scirxbuf.all; Read data from FIFO to cache

}

Scicregs.scifftx.bit.txffintclr=1; It is important that if you do not clear the FIFO Send interrupt flag, do not enter the send interrupt

Scicregs.sciffrx.bit.rxffintclr=1; Clear receive interrupt Flag

PIECTRLREGS.PIEACK.ALL|=PIEACK_GROUP8; Issue PIE ack

}

void Scib_fifo_init ()

{ScicRegs.SCICCR.all =0x0007; 1 Stop bit, No loopback

No parity,8 Char Bits,

Async mode, Idle-line Protoco

ScicRegs.SCICTL1.all =0x0003; Enable TX, RX, internal SCICLK,

Disable RX ERR, SLEEP, Txwake

Scicregs.scihbaud =0x0001;

Scicregs.scilbaud =0x00e7; Baud Rate 9600

ScicRegs.SCIFFTX.bit.SCIFFENA = 1;//Enable SCI FIFO function

ScicRegs.SCIFFTX.bit.TXFFIENA = 1;//fifo Send interrupt Enable

ScicRegs.SCIFFTX.bit.TXFFIL = 0; Send interrupt level, at which time the power-on default value is 0

ScicRegs.SCIFFRX.bit.RXFFOVRCLR = 1;//clear receive FIFO overflow flag

ScicRegs.SCIFFRX.bit.RXFFINTCLR = 1;//Clears the receive FIFO interrupt flag bit

ScicRegs.SCIFFRX.bit.RXFFIENA = 1;//Enable FIFO receive interrupt

ScicRegs.SCIFFRX.bit.RXFFIL = 8; FIFO receive interrupt level of 8

scicregs.sciffct.all=0x00; The default effect is to disable automatic baud rate adjustment FIFO delivery delay of 0

scicregs.scifftx.bit.txfifoxreset=1;//re-enable to send FIFO operation

scicregs.sciffrx.bit.rxfiforeset=1;//re-enable receive FIFO operation

ScicRegs.SCICTL1.all =0x0023; Relinquish SCI restart SCI from reset

}

28335scififo interrupt Receive and send