(4) 7-bit slave address of I2C bus

Clock stretch (clock stretching)
Clock stretching suspends a transmission by lowering the SCL line. the transfer will not continue until the release of the SCL line is high. clock stretching is optional. In fact, most slave devices do not include the SCL driver, so they do not support the stretch clock.
From the byte level, a device may accept data in fast mode, but it takes more time to store the received bytes or prepare another byte to be transmitted. the slave machine can use a handshaking method to lower the SCL line after receiving and responding bytes to force the host to enter the Wait Status and know that the slave machine has prepared the next byte transmission.
In bit level, devices on the I2C bus can reduce the bus clock by increasing the low cycle of each clock, so each host can adapt to the internal operation rate of the device.
In HS mode, handshaking can only be used at the byte level.

Slave address and R/W Bit
Is the data transmission format:

After the start condition (s), the sending slave address. The address is 7bit, And the 8bit is the data read/write bit. 0 indicates writing, and 1 indicates reading. For details, see:

The termination condition (p) generated by the host for data transmission. However, the host can also generate a duplicate start condition (SR) and address another slave without having to generate a termination condition first,
Possible data transmission formats are as follows:
The Master-transmitter transmits data to the slave-receiver. The transmission direction remains unchanged. The slave-receiver replies to each byte as follows:

The Host reads data from the slave after the first byte. after the first response, the master-transmitter changes from the receiver to the master-receiver. the first response is still generated by the slave server. the host generates the remaining response. the host sends a na before the termination condition is generated. as follows:

Composite mode. during transmission, the start condition and slave address must be the same, while the read/write bit must be reversed. if the master-receiver sends a duplicate start condition, it will send a na before that.

Note:
1. the composite mode can be used to control the serial memory, for example. when writing the first Data byte, you must write the internal address of the memory. when the start condition and the slave address are repeated, data is transmitted.
2. It is determined by the device designer to automatically increase or decrease the memory locations previously accessed.
3. Each byte is followed by a response bit, which is represented by a or not a in the figure.
4. devices compatible with the I2C bus must restart their bus logic when receiving the start condition or repeating the start condition, even if the start condition is not in the correct format, they all expect to send the slave address.
5. It is illegal to immediately follow the termination condition after the start condition. Many devices can solve this problem when designing.
6. each device connected to the bus is determined by a unique address. it is usually a simple master-slave relationship, but there may be multiple identical slaves that can receive and respond at the same time, such as multicast. here is an example of NXP pca9546a. (pca9546a is a four-channel bidirectional multiplexing and switch developed by NXP semiconductor Based on I2C bus control. You can use pca9546a to extend the input of one-way SCL/SDA to four-way SCL/SDA output. After configuring the internal control register, one or more downstream I2C buses can be selected to communicate with the upstream I2C bus at the same time .)