About PCIe's memo

Bus driver: Depth-priority statistics resource, deep lag resource allocation

Resource contains bus ID and memory (prefectable and non-prefectable memory)

Device driver: Includes device driver layer and message communication

The main is four parts:

(1) Interrupt: EP to RC interrupt, MSI

(2) RC to EP interrupts, MSI (some EP not supported) or other internal interrupts

Inbound and outbound take the following model as an example:

[RC]<-INBOUND<-[SW]<-OUTBOUND<-[EP]

(3) Inbound: To the end of the set, I want to be peer-to-peer access, the RC side will BAR3 address inbound over to the RC end of a memory

This modifies the contents of the BAR3 corresponding to the EP end, then the contents of the RC side memory are changed.

(4) Outbound: Local settings, I want to access those addresses, set the address to the end of the outbound register, modified on the EP side, the RC side content changes

About PCIe's memo