Alicloud designer rule settings

Design Rule settings designer rules check (DRC)

Electrical electrical rules. Security spacing, network connection, etc.

Routing wiring, line width, shape and size of passing holes, wiring topology, wiring layer, package outlet, etc.

SMT surface mount technology, surface assembly technology (Surface Mount Technology), SMD. Requirements of pad for SMD components

Mask mask, solder mask and solder paste Extension

Plane inner electrical layer and copper pad. Connection Mode with pad

Testpoint test point

Manufacturing Processing. Dimensions and relationships of holes, pad, silk screen and solder Resistance

High-speed signals of highspeed. High-speed signals such as crosstalk, line length, configuration length, and number of passing Holes

Placement. Component placement and component spacing

Signalintegrity signal integrity. Line impedance and high-speed signal overshoot, pendulum rate, etc.

 

The same rule can contain (new) multiple rules, and set different use scopes and priorities for each rule to implement flexible and diverse rules as needed.

Set priority: in the lower-right corner of the dialog box, enter priorities.

Import rule. rul File

 

Details:

Clearance safe distance, including the minimum distance between component pad and pad, pad and wire, and wire

Short Circuit short circuit, and whether to allow cross-Short Circuit of the wire. It is not allowed by default.

Un-connect net is not connected to the network. You can specify the network and check whether the network wiring is successful.

Un-connected pin is not connected. check whether all element pins are connected to the specified network.

 

Width wire width

Routing toplogy cabling topology. Topology rules are defined based on the topological logic constraints of cabling. Common wiring constraints are the minimum statistical logic rules. You can select different wiring topology rules based on the specific design:

Shortest shortest

Horizontal horizontal rule settings, the Minimum horizontal line rule of the connected nodes

Vertical vertical rule setting: the shortest rule for the vertical line of the connected Node

Daisy simple daisies rule settings, using the chained connection rule, connect all nodes from one point to another, and make the connection shortest

Daisy-middriven daisies midpoint rule settings, select a source point, it as the center to connect all nodes left and right, and make the connection shortest

Daisy balanced daisies balancing rule settings, select a source point, divide the number of all intermediate nodes into groups equally, all groups are connected to the source point, and make the connection shortest

Select a source point for the star burst (STAR) Rule settings, connect other nodes in star form, and make the connections shortest.

 

Routing priority cabling priority

Routing layers cabling layer settings

Not used this layer is not cabled;

Horizontal this layer is horizontally routed;

Vertical this layer is vertically routed;

Any this layer can be cabled in any direction;
10n clock this layer is wired at one o'clock;
20n clock: This layer is cabled at two o'clock;
40n clock this layer is wired at four o'clock;
50n clock this layer is wired at five o'clock;

45up this layer is for cabling up to 45 °,

45 down this layer is laid down by the 45 ° method;

Fan out this layer is cabled in slice mode.

For the default dual-Panel, one side of the wiring adopts the horizontal mode, and the other side adopts the vertical mode.

 

Routing corners corner. 45, 90, rounded corner

Routing via style guide hole.

 

Welding Assembly Layer Design Rules

Solder Mask expansion welding layer extends. It is used to design the distance between the welding layers. When making a circuit board, the welding layer should reserve some space for the welding pad. This extension is to prevent overlap between the welding pad and the welding pad.

Paste mask expansion Surface adhesive Element Extension. Distance between Solder Pad and solder layer hole of Surface adhesive Element

 

Inner Design Rules plane for Multilayer

Power plane connect style power layer connection mode. Used to set the connection from the guide hole to the power supply Layer

Conner style drop-down list. Set the connection style between power supply layer and guide hole

Relief connect divergent connection

Direct Connect

No Connect is not connected

Conductor width: sets the width of the on-going wire.

Number of connected wires selected by conuctors

Air-gap: Set the gap width

Expansion sets the distance from the guide hole to the Gap

Security distance between power plane clearance power layer. Sets the safe distance between the power supply layer and the guide hole passing through it, that is, the minimum distance between the broken wires.

 

Polygon connect style copper binding connection method. Connection Mode between polygon copper and pad

Connect style, conductors, and conductor width

Connection Angle Between Copper pad and pad: 90, 45

 

Test Point design rules are used to design the shape and usage of test points

Testpoint style test point style.

Size the size of the test point

Grid size

Allow testpoint under component select whether to allow the test point to be placed under the component

 

Usage of testpoint usage test point

Allow multiple testpoints on same Net Setting whether multiple test points can exist on the same network

The single option in the testpoint option area selects the processing of the test point, so that required (mandatory), invalid (invalid test point), don't care (negligible test points)

 

Circuit Board Design Rules

Manufacturing

Min imum annular ring minimum pad Ring Width

Acute angle wire angle settings

Hole Size guide hole diameter settings

Measurement method: absolute is designed in absolute size; percent is designed in relative proportion

Layers Pais uses a half-layer pair. If a blind guide hole is used in the design of a multi-layer board, you must set the layer here.

 

 

 

 

 

 

 

 

Design Rule Check

Alicloud designer rule settings