Android automatically identifies the memory size

1. Relationship between memory hardware structure and addressing of MINI6410

After reading the above documents, I believe we should have a complete understanding and understanding of the DDR memory. Let's talk about the memory hardware structure on MINI6410:

For the MINI6410 design, two pin-compatible DDR memory chips are used to achieve MB memory and MB memory sharing a PCB.
MB memory uses two pieces of k4x000063pg32mx16bit) to form a 32 m × 32bit128MB memory. MB memory uses two pieces of K4X1G163PE64Mx16bit) to form a 64M × 32bit256MB memory. The difference between the two chips is that the F7 of k4x201763pg is the NC foot, while the F7 foot of K4X1G163PE is A13. The F7 pin is not connected in the MINI6410 of the mb memory version, while in the MB version, it is connected to the Xm1ADDR13 of the euro resistance.

Those who read the data manuals of these two memory chips and the cloud6410dram controller must know that this connection forms an addressing relationship like this:

MB memory version: Xm1ADDR [] bank): Xm1ADDR [12: 0] row address): Xm1ADDR [] column address ). A total of 25 address lines can address 32 m space. MB memory version: Xm1ADDR [] bank): Xm1ADDR [13: 0] row address): Xm1ADDR [] column address ). A total of 26 address lines can address 64 m space. These two types of connections and chip configurations must also be matched by modifying the parameters of the two registers of the DRAM controller.

2. Position of Adaptive Memory code in U-boot
 
After preparing the above two knowledge items, let's take a look at the locations in u-boot to identify and adapt to different memory sizes.
First, after recognizing the memory size, we may need to reconfigure the memory controller of the processor. In this way, the Code cannot be run in DDR. Once the memory controller is reconfigured, the memory will be temporarily unavailable. If the code is in the DDR, the CPU may not be able to get the next code. Therefore, these codes should be placed in the place where u-boot implements the self-copy to the memory. In fact, the best place is to initialize the memory controller code segment in the SPL part of u-boot.

These codes are available in: arch/arm/cpu/arm1176/cloud64xx/cpu_init.S.

This file is assembly code. The mem_ctrl_asm_init function is called through "bl lowlevel_init" ------>/board/samsung/mini6410/lowlevel_init.S "lowlevel_init" bl mem_ctrl_asm_init "in start. S. The code in the mem_ctrl_asm_init function initializes the DRAM controller of and the external DDR memory. Therefore, the memory recognition and adaptive code should be placed after the initialization. First, identify the memory size. If the memory size does not match the original DRAM controller configuration, modify the DRAM controller configuration.

3. Memory size Recognition

For MINI6410, we only need to identify whether the memory is 256 MB or MB. Because the two memory sizes are related to the parameters of the two registers of the DRAM controller, we must first assume our memory size and then prove it through the read/write method, if our assumptions are proved to be incorrect, modify the register parameters.

In the transplanted U-boot code, we first assume that the memory is 256 MB, and first configure the DRAM controller as the parameter of MB memory. If the connection is MB memory, there will be an interesting phenomenon:

Because Xm1ADDR [13] is not connected, the first 8M × 32bit32MB of the DDR memory and the second 8M × 32bit32MB) are mirror relationships, and the third 8M × 32bit32MB) and the fourth 8 Mb × 32bit32MB) is the image relationship, and so on. There are a total of four such image relationships, totaling 256 MB. If the connection is MB memory, this will not happen. Therefore, as long as we prove the existence of this phenomenon, it proves that we are actually connected to the MB memory, and then reconfigure the DRAM controller to set the parameter to MB memory.

Therefore, in the transplanted U-boot code, first write a 32bit test data to a location such as 0x0 In the first 8 m × 32bit32MB), and then go to the second 8 m × 32bit32MB) if the data is consistent, the image relationship can be proved. But it is not safe yet. If it happens to connect to the memory of MB) The second 8 Mb × 32 bit32mb) is the data itself. What should I do? It doesn't matter. Let's go to the second 8 m × 32bit32MB) to write another test data at the same location, and then read the data at the first 8 m × 32bit32MB, if the data is consistent, the image relationship can be proved completely. Through these two tests, you can see if you want to reconfigure the DRAM controller parameters.

However, we cannot assume that the memory is 128 MB, and first configure the DRAM controller as the parameter of MB memory. If the connection is MB memory, no special phenomenon can be tested. Through the above addressing relationship, if the connection is MB memory, but the second, fourth, sixth, and eighth assume Xm1ADDR [13] has been 0) 8 Mb × 32bit32MB) is inaccessible, it can be said that the memory is empty), this can not pass the Read and Write proof. Inferred by addressing relationship, not proved by experiment)

4. reconfigure the Memory Controller

If the image exists in the above steps, we must reconfigure the values of the two registers, but how to reconfigure it is not described in this Samsung Data Manual, I tested and found that the DRAM controller can be reconfigured through the following steps:

1. Set the DRAM controller to pause Paused;

2. Check P1MEMSTAT until Paused is Paused;

3. Set the DRAM controller to the Config state;

4. Check P1MEMSTAT until the Config configuration is confirmed;

5. Modify the register to be reconfigured

6. Set the DRAM controller to the Go startup status;

7. Check P1MEMSTAT until the Ready is confirmed;

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