Android deep exploration and HAL-driven development (Volume 1)-Chapter 5: android-driven development

Android deep exploration and HAL-driven development (Volume 1)-Chapter 5: android-driven development

Reduced instruction set computer (balanced CED instruction set computer)

 

Introduction

A simplified Instruction Set is a design model of the Computer's central processor. It is also known as the short form of the Reduced CED Instruction Set Computer ). [1] This design concept simplifies the number of commands and addressing methods to make it easier to implement. The parallel execution of commands is better, and the compiler is more efficient. Commonly used streamlined Instruction Set microprocessors include DECAlpha, ARC, ARM, AVR, MIPS, PA-Proteus, PowerArchitecture (including PowerPC), and iSCSI. This design concept was first originated from the discovery that although traditional processors have designed many features to make code writing more convenient, these complex features require several instruction cycles for implementation, it is often not used by running programs. In addition, the speed difference between the processor and the main memory is also growing. Driven by these factors, a series of new technologies have emerged, allowing the processor to execute commands in a streamlined manner and reducing the number of times the processor accesses the memory. In the early days, this instruction set was characterized by a small number of commands. Each instruction was made visible to machine-level programs with long standard words, short execution times, and central processor implementation details.

 

Development Prospects

In view of the design features and unparalleled advantages of the Proteus architecture processor, the development direction of the Proteus architecture processor is as follows:
First, increase the concurrency of the processor;
Second, expansion supports the functions of Scalable Parallel Computer Systems;
Third, improve the process level. In the end, the perfect integration of the server-side CPU and DSP in embedded applications is inseparable.
In addition to streamlining the instruction system, the Proteus microprocessor uses over-standard and over-pipeline structures. The number of instructions is only several decades, but the parallel processing capability is greatly enhanced. For example, in 1987, SunMicrosystem launched the iSCSI chip, which is a type of high-capacity, high-performance, and high-performance CPU. The MIPS processor launched by SGI uses a hyper-pipeline structure, which plays a core role in the construction of parallel, streamlined command system multi-processor. Modern 64-bit multi-processor is a mainstream chip in the UNIX field.

 

Performance Characteristics

1. After the instruction set is simplified, pipelines and Common commands can be executed in hardware;
2. A large number of registers are used to enable most command operations between registers, improving the processing speed;
Iii. the cache-host-external storage three-level storage structure is used to separate the fetch and storage commands, so that the processor can do as much work as possible, the processing speed is not slowed down because the information is accessed from the memory.

 

Application features

Due to the simple instruction, hardware and wiring control logic, strong processing capability, and high speed of the server, the vast majority of UNIX workstation and server vendors in the world use the CPU with the chip. For example, Alpha21364 of DEC, PowerPCG4 of IBM, PA-8900 of HP, R12000A of SGI and UltraSPARC compiler of SUNMicrosystem.

 

Features

The operating frequency of a chip is generally MHz. The low clock frequency, low power consumption, and low temperature rise make it difficult for machines to malfunction and age, improving system reliability. A single command cycle supports multiple parallel operations. In the process of developing the Proteus microprocessor. A vliw microprocessor was created, which uses a very long command combination to connect many commands for parallel execution. The basic model of the VLIW processor is the execution model of scalar code, so that there are multiple operations in each machine cycle. Some also use a few VLIW commands to improve processing speed.