There are 6 major classes of ARM processor instruction sets:
- Jump Instructions
- Data processing Instructions
- Program Status register (PSR) processing instructions
- Load/Store Instructions
- coprocessor directives
- Exception generation Instructions
| Instructions |
Command function |
| Adc |
With carry addition |
| ADD |
Addition |
| and |
Logic and |
| B |
Jump |
| BIC |
Bit zeroing |
| BL |
Jump with Return |
| BLX |
Jump with return and status toggle |
| Bx |
Jump with status Toggle |
| Cdp |
Co-processor data operations |
| CMN |
Compare Inverse values |
| Cmp |
Comparison |
| Dos |
XOR or |
| LDC |
Data transfer from memory to coprocessor |
| Ldm |
Loading multiple registers |
| LDR |
Memory-to-register data transfer |
| Mcr |
Data transfer from ARM registers to coprocessor registers |
| MLA |
Multiply add operation |
| MOV |
Data transfer |
| Mrc |
Data transfer from coprocessor registers to arm registers |
| MRS |
Transfer the contents of CPSR or SPSR to the general register |
| Msr |
Transmit general-purpose registers to CPSR or SPSR |
| MUL |
32-bit multiplication |
| MVF |
Transfer value to floating point register |
| MVN |
Data Reverse Transfer |
| ORR |
Logical OR |
| RSB |
Inverse subtraction |
| Rsc |
Inverse subtraction with borrow |
| Sbc |
With borrow subtraction |
| Stc |
Coprocessor Register Write storage |
| Stm |
Bulk Memory Word Write |
| Str |
Register-to-memory data transfer |
| SUB |
Subtraction |
| Swi |
Software interrupts |
| TEQ |
Equality test |
| TST |
-Bit testing |
|
|
ARM Command addressing Mode
1. Immediate number addressing
The operand is given in the instruction, and as soon as the instruction is taken, the operand is taken, and the operand becomes an immediate number.
ADD R0, R0, #1; R0 <-R0 + 1
ADD R0, R0, #0x3A; R0 <-R0 + 0x3A
In the above instruction, the 2nd source operand is an immediate number.
2. Register addressing
Register addressing, which uses the value in the register as the operand.
ADD R0, R1, R2; R0 <-R1 + R2
This instruction will register the contents of R1 and R2, the result exists in R0.
3. Register Indirect addressing
The register indirection is the address of the operand as the value in the register, and the operand itself is stored in memory.
ADD R0, R1, [R2]; R0 <-R1 + [R2]
LDR R1, [R1]; R0 <-[R1]
1th instruction, the contents of the Register R2 as the address of the operand, and then add to the R1, the result is deposited in the Register R0.
The 2nd instruction is sent to R0 in the contents of the register with the R1 value as the address.
4 Address addressing
The address of a base address is addressed by adding the contents of the register (commonly referred to as the base address register) to the offset of the addresses given in the instruction, thus obtaining a valid address for the operand.
LDR R0, [R1, #0x0A]; R0 <-[R1 + 0x0A]
LDR R0, [R1, #0x0A]!; R0 <-[R1 + 0x0A], R1 <-R1 + 0x0A
1th instruction, the contents of the Register R1 plus 0x3A form the operand valid address, and then send the operand at that address to R0.
2nd instruction, the contents of the Register R1 add 0x3A to form the operand valid address, and then the number of operations at that address to R0, and finally R1 + 0x0A value is saved to R1, R1 is updated.
5. Multi-Register addressing
Multi-register addressing, a single instruction can complete the transfer of multiple register values. This type of addressing can be played as a single instruction to transmit a value of up to 16 universal registers.
Ldmia R0, {R1, R2, R3,R4}; R1 <-[R0]
; R2 <-[R0 + 4]
; R3 <-[R0 + 8]
; R4 <-[R0 +]
The suffix IA of this directive is the meaning of "Increment after", which means that after each load/store operation, the R0 is incremented by the length of the word, so the instruction can transfer the value of the contiguous storage unit to R1~R4.
6. Relative addressing
Similar to the base address, relative addressing takes the current value of the program counter PC as the base, and the address designator in the instruction as an offset, adding the operands as a valid address.
BL Next; jump to sub-program next place execution
... ...
NEXT
... ...
MOV PC, LR; Returning from a child program
7. Stack addressing
Depending on how the stack is generated, the stack is divided into an incrementing stack (ascending stack), and a descending stack (decending stack), called the increment stack when the stack is generated from a low address to a high address, and when the stack is generated by a high address to a low address, called a decrement stack. This way, there are 4 ways to stack work:
(1) Full increment stack: the stack pointer points to the last pressed data, and the stack is generated incrementally.
(2) Full decrement stack: the stack pointer points to the last pressed data, and the stack is generated in descending form.
(2) Empty increment stack: the stack pointer points to the next empty location where the data will be placed, and is generated from the low address to the high address.
(3) Empty decrement stack: the stack pointer points to the next empty location where the data will be placed, and is generated from a high address to a low address.
ARM instruction Set
