Asynchronous Reset and synchronization release

I. Advantages and Disadvantages of synchronous and asynchronous resetting:

(1) Synchronous Reset:

Advantages: synchronization with the clock greatly reduces the probability of sub-steady state;

Disadvantage: it consumes logical resources in the disk;

always@(posedge clk)    if(!rst_n)        a <= 1‘b0;    else        a <= b;

Synchronous Reset

(2) Asynchronous Reset:

Advantage: using the clear end of FPGA internal registers does not increase unnecessary logic consumption;

Disadvantage: it is prone to sub-steady state, which exists between Asynchronous Reset and clock;

always@(posedge clk or negedge rst_n)    if(!rst_n)        a<= 1‘b0;    else        a<= b;

Asynchronous Reset

Asstable state generated by Asynchronous Reset:

always @ (posedge clk or negedge rst_n)    if(!rst_n)         b <= 1‘b0;    else         b <= a;always @ (posedge clk or negedge rst_n)    if(!rst_n)         c <= 1‘b0;    else         c <= b;

Dangers of Asynchronous Reset

Note:Under normal circumstances, CLK's rising edge C is updated to B, and B is updated to. Once reset is enabled, both B and C are cleared. However, we cannot determine when the reset signal rst_n will end. If the {launch edge-stup at B _reg0 and c_reg0 end, and the launch edge + hold} time is only exceeded, everything will be normal. But if it is the opposite, what will happen? The rise of rst_n occurs at the build-up holding time of CLK rise. At this time, the state of rst_n detected by CLK is a sub-steady state (0 is 1 ). From the code, we can see that if B _reg0 and c_reg0 think that rst_n is 0 at this time, the reset is still cleared. If rst_n is regarded as 1, the reset is skipped. Due to the uncertainty of rst_n at this time, four situations may occur: Both B _reg0 and c_reg0 reset or both jump out of the reset, or one reset and one jump out of the reset. The latter will cause the problem of system operation non-synchronization. In this simple two-level Asynchronous Reset instance, this hazard is not obvious, but let's think about how many registers in a large engineering project will look like this?

2. Because both synchronous and asynchronous reset have some defects, most engineers now adopt another reset method called "Asynchronous Reset, synchronous release ", combined with the advantages of the two, the main idea is asynchronous signal synchronization.

1 always @ (posedge CLK) 2 rst_nr <= rst_n; // now sets the Asynchronous Reset signal to a synchronous clock for a shot 3 4 always @ (posedge CLK or negedge rst_nr) 5 If (! Rst_nr) 6 B <= 1 'b0; 7 else 8 B <= A; 9 10 always @ (posedge CLK or negedge rst_nr) 11 if (! Rst_nr) 12 C <= 1 'b0; 13 else 14 C <= B;

Asynchronous Reset and synchronization release

Asynchronous Reset and synchronization release