Basic knowledge of Cortex-M3 registers

1. Register

Cm3 has R0 ~ R15 General registers and some special function registers

R0 ~ R12 these general registers, the initial reset values are unpredictable

2. cm3 has a general register group from R0 to R15

Note: The vast majority of 16-bit thumb can only access R0 to R7, while 32-bit thumb-2 can access all registers.

3. Special Function registers

3.1 Program Status Register Group)

3.2 interrupt shielding register group: used to control the Energy Division and enable of exceptions

3.3 control register: used to define the privileged level and the stack pointer currently used

4. Operation Mode and privilege level:

Two operation modes: Handler mode and thread mode (used to distinguish the code of abnormal service routines from the code of Common Programs)

Two levels of privilege: privileged level and user level (refers to the setting of the storage access permission on the hardware level)

Note: cm3 can use the privileged level and user level when running the main program (namely the thread mode), but the exception service routine (I .e. the handler mode) can only use the privileged level, here is the conversion of various operation modes.

Basic knowledge of Cortex-M3 registers