BSIM3 Study Notes 4

Capacitance model

Depending on the magnitude of the time-varying voltages, the dynamic operation can be classified as large sig NAL operation or small signal operation.

A capacitance model describing the intrinsic and extrinsic components of the device capacitance, are another essential part A compact MOSFET model for circuit simulation besides the DC model.

Generally, MOSFET capacitance can be divided into and groups, the intrinsic and the extrinsic capacitances.

The intrinsic capacitance is related to the region between the metallurgical source and drain junctions.

The extrinsic capacitance, or the parasitic capacitance, is further divided to five components:

1) The outer fringing capacitance between the polysilicon gate and the Source/drain, C-FO;

2) The inner fringing capacitance between the polysilicon gate and the Source/drain, CFI;

3) The overlap capacitances between the gate and the heavily doped s/d regions (and the bulk region), CGSO /c5>& cGDO (cGBO), which is relatively insensitive to terminal voltages;

4) The overlap capacitances between the gate and lightly doped s/d region, Cgsol & CGD OL , which changes with bias;

5) The Source/drain junction capacitances, CJ D & CJS.

intrinsic capacitance: use Meyer model (large signal models)

Shortcoming of the Meyer model

1. It had been found to yield non-physical results when used to simulate circuits that had charge storage nodes.
2. Charge built-up on these nodes is incorrectly predicted by the simulation. This problem shows-in MOS charge pumps, Silicon-on-sapphire (SOS) circuits, static RAM and Switched-capacitor circuits. It is termed the charge non-conservation problem.

extrinsic capacitance Model :

Add up the Cfo,cfi,cov to be covt. is the external capacitor.

The above model is not suitable for short channel devices.

So with Bsim There are three of them, three of them are not written. I'll look at it later with that!

BSIM3 Study Notes 4