Clock Gate cell

The cell of clock gate uses the form of latch, to realize, avoid glitch produce as much as possible.

Possible Verilog modeling methods:

Module Cell_ckgate (TE,E,CP,Q)

Input TE;

Input E;

Input CP;

Output Q;

Wire e_or;

Wire E_lat;

Assign e_or = E | TE;

Always @ (CP or e_or)

if (! CP) begin

E_lat <= E_or;

End

Assign Q=e_lat & CP

Endmodule

Latches are only possible when the CP is low, so the value of enable can be introduced, so the clock behind the final gate has a full rising and falling edge of half cycle.

Clock Gate cell