Common serial communication Protocols

1.UART

UART is a universal asynchronous transceiver, using RXD and TXD two cable to achieve asynchronous full-duplex communication, in order to ensure reliable communication, can be connected on both sides of the communication, so the complete UART communication requires a minimum of 3 lines.

RXD is the transmission of data lines, TXD is to receive data lines, communication between the two sides using cross-interconnect, rxd to each other txd,txd pick up each other rxd. The UART uses a standard Ttl/cmos level (0~5v,0~3.3v,0~2.5v,0~1.8v) to represent the data, a high level of 1, and a low level of 0. To enhance the anti-jamming capability and increase the transmission length, the Ttl/cmos level can be converted to the RS232 level logic level. 3~12V indicates that 0,-3~-12V represents 1 (RS232 is negative logic)

1) UART usually in idle state, logic 1 state.

2) When there is data sent, first send the starting bit, will be txd low and maintain 1-bit time, the receiver detects the starting bit falling edge, waiting for 1.5 bit after the start of a test data.

3) Send data, the UART data frame can be 5,6,7,8 bits, etc., is generally 8bit, a byte. Data send is sent low, then sent, until the highest bit.

4) 0 or 1bit check digit can be used, check digit can be odd or even test. Odd check: The number of 1 in the data plus check bit is odd; parity: The number of 1 in the data plus check bit is even.

5) Finally the stop bit, the data line reverts to the idle state, the stop bit can be the 1,1.5,2 bit.

1-bit time is determined by the baud rate, in the UART communication, the baud rate (the number of symbols transmitted in a second) is equal to the bit rate (the number of characters transmitted in a second), the communication parties using the agreed baud rate of communication, the common baud rate has 4800,9600,115200 and so on.

2.i2c

Unlike the UART, I²c is a synchronous half-duplex communication protocol. I²c uses SCL,SDA two bidirectional data cable for communication, while the open-drain output is required to support line and logic, using the pull-up resistor Pull-up resistor size common 1.8k,4.7k,10k, in low-speed situations, in order to reduce power consumption, you can use the 10K pull-up resistor, 1.8K pull-up resistor with the best performance, to meet the high-speed applications. Common communication rates are normal: 100K, fast: 400K, High speed: 3.4M. The maximum number of slave machines is limited by the slave address and the maximum bus capacitance of 400pF capacitance. The data frame format for I²c is as follows:

Start bit | 7bit Slave Address | 1bit read/write direction bit (0 write, 1 read) | 1bit Response | 8bit Data 1 | 1bit Answer 1| ...  | 8bit Data n |1bit non-response n | Stop bit.

Idle state: When idle, the SCL,SDA is at high level. At this point, the output FET of each device is in the cutoff state, releasing the bus, the bus signal from the pull-up resistor up to high level.

When the START:SCL starts to high, SDA has a falling edge.

Data transfer: The data transfer is in bytes, the first byte represents the slave address + read/write direction, and subsequent data formats are defined by the device itself. In data transmission, SDA can only change at the SCL low level, and the data is sampled on the SCL rising edge.

Answer: After each byte is sent, the receiver must reply to the signal ACK, but after sending the last byte, return the non-response signal nack.

When the stop STOP:SCL is high, SDA has a rising edge.

Handshake mechanism: I²C provides a handshake mechanism that, when the host is too fast to meet fast communication from the machine, the slave can pull down the SCL to handshake with the host, thereby prolonging the SCL low level. (The SCL high is determined by the shortest high level for all devices, and the low level has the longest decision at the low level.)

Quorum: SDA is a line and logic, so as long as one end of the output is low, the bus is low and therefore a low-level priority quorum. The quorum rule is to send a host with a number of low levels to get the bus right.

Due to the directivity of the i²c communication, the data flow direction cannot be changed in a single communication, so a dummy writing process is required during the reading process:

Dummy after writing, in the restart, then the data flow direction to read, and then you can read the slave data content.

3.SPI

SPI is a synchronous full-duplex serial communication protocol. The SPI defines 4 signal lines:

SCK: Clock line, Host provides

Miso: Primary in Slave out

MOSI: main out from into

SS: Film Selection.

The chip selection signal is optional, so communication requires a minimum of 3 signal lines. SPI in the clock rising along the two-way data exchange, the host in the output, but also receive the data from the machine. In the design, a shift register is required for the host slave machine. SPI does not distinguish between read and write direction, only the data exchange, to read also must write, in order to exchange data over.

The SPI defines 4 communication modes via clock polarity and clock phase:

Clock polarity cpol:0: sck at idle is 0, 1: sck is 1 when idle.

Clock phase cpha:0: Data is sampled on the first clock hop (may be rising edge, may be falling edge, associated with Cpol), 1: Data is sampled on the second clock hop (may be rising edge, may be a falling edge, related to Cpol).

If the upper edge is sampled, the data is output at the bottom edge, so the data can be sampled stably.

The SPI timing diagram is as follows:

Common serial communication Protocols