Compilation--Second lecture

Central Processor CPU

The microprocessor is abstracted as a register that is accessed by name.

It mainly contains the arithmetic and controller of instruction execution, as well as a variety of registers.

CPU operating mode

1 Real Mode

2 protection mode

3 Virtual 8086 mode

8086/8088 of functional structure

Module one, bus interface unit Biu, mainly responsible for reading instruction and operation number.

Module Two, the implementation unit EU, mainly responsible for instruction decoding and implementation.

Execution period of the instruction:

1. Take instruction

2. Decoding

3, take the operation number

4. Implementation

5. Storage output Operation number

16-bit Registers

The segment register is a dedicated register dedicated to memory addressing. The starting address where the logical segment is stored.

Code segment data segment stack segment extra segment

32-bit Registers

Expanded 2 16-bit segment registers : FS and GS

Data registers

Pointer Register SP/BP

Variable address register Si/di

Instruction Pointer IP

Carry register CF (carry flag) when the addition (subtraction) of the operation, if the highest bit forward has a (borrowing) bit, then cf=1, otherwise cf=0.

0 flag-bit ZF (zero flag) when the operation result is zero zf=1, otherwise zf=0.

The symbol mark bit SF (sign flag) when the highest bit of the result of the operation is 1 o'clock sf=1, otherwise sf=0.

Parity flag bit PF (Parity flag) when the number of "1" in the lower 8 bits of the operation result is even when pf=1, is odd, pf=0

Overflow flag OV (Overflow flag) When the result of the arithmetic operation is outside the range of the signed number, i.e. overflow, of=1, otherwise of=0

Compilation--Second lecture