Convolution design Note 2

After several days of debugging, the program has finally been optimized. After debugging, I found that I still had a weak foundation and didn't have a good reading experience. I felt like I had to take a good look at Xia Yuwen's book. "If the register group is both input and output under the positive hop of the same clock, it is likely that the input condition is not determined due to the delay of the gate, output the next state, which may cause logical disorder. However, it is safe and reliable to use the previous clock to create trigger conditions for the next clock. In the implementation of the actual circuit, many effective measures have been taken to ensure the establishment: 1. Global clock network wiring should try to make the clock of each branch consistent. 2. Use a Balance Tree Structure and add a buffer at each level to synchronize the clock at each trigger ."

In the ram_read state of my program, I assign values to ram_output_data and rom_output_data, and perform operations on them, resulting in a data delay.

 1                 ram_read: begin     2                         if (ROM_count <= count3)    begin         3                             RAM_ADDR_R <= count2; 4                             ROM_ADDR <= ROM_count; 5                             ram_output_data <= ram_output; 6                             rom_output_data <= rom_output; 7                             da_data_ <= ram_output_data * rom_output_data + da_data_; 8                             if (count2 == 0) begin 9                                 10                             end11                             else begin12                                 count2 <= count2 - 1;13                             end14                             ROM_count <= ROM_count + 1;15                             state <= ram_read;16                         end17                         else state <= state_data_output;18                     end19                 state_data_output: begin20                         da_data <= da_data_[31:16] + 16‘d32767;21                         state <= ram_write;22                     end23                 default: state <= ram_idle;24             endcase        25     end    

Previous ram_read status

After assigning values and calculating values in two states, the data is delayed, but the previous data is still computed. In Xia Yuwen's book, we can see that the non-blocking value assignment is first stored in a hidden register. When the next clock comes to the output, the data is calculated for the first time or stored for the last time, therefore, after caching the ram and Rom addresses, the result is correct.

 1                 ram_write: begin 2                         if (ad_clk_pos) 3                            begin 4                                 RAM_ADDR_W <= count1; 5                                 ram_wr <= 1‘b1;     6                                 da_data_ <= 32‘d0;     7                                 count4 <= 16‘d0; 8                                 ROM_count <= 5‘d0; 9                                 ram_output_data <= 16‘d0;10                                 rom_output_data <= 16‘d0;                            11                                 ram_data <= ad_data - 16‘d32767;12                                 state <= ram_count;13                             end14                         end15                 ram_count: begin16                             if (count1 == 16‘d31)    begin                                    17                                 count2 <= count1;18                                 count3 <= count1;19                                 count1 <= 16‘d0;20                             end21                             else    begin22                                 count2 <= count1;23                                 count3 <= count1;                                    24                                 count1 <= count1 + 16‘d1;                                                                        25                             end26 //                            RAM_ADDR_R <= count2;27 //                            ROM_ADDR <= ROM_count;                                                28                             state <= ram_WR_END;29                            end30                 ram_WR_END:    begin31                         ram_wr <= 1‘b0;32                         state <= ram_wait;33                     end34                 ram_wait: begin35                             RAM_ADDR_R <= count2;36                             ROM_ADDR <= ROM_count;37                             state <= ram_read;38                     end39                 ram_read: begin    40                         if (ROM_count <= count3)    begin    41                                 RAM_ADDR_R <= count2;42                                 ROM_ADDR <= ROM_count;43                                 state <= ram_dddd;44                         end45                         else state <= state_data_output;46                         47                     end48                 ram_dddd: begin49                         if (count4 == 2)    begin50                             count4 <= 16‘d0;51                             state <= ram_delay;52                         end53                         else    begin54                             count4 <= count4 + 1;55                             state <= ram_dddd;56                         end    57                     end58                 ram_delay:begin59                         ram_output_data <= ram_output;60                         rom_output_data <= rom_output;61                         state <= ram_process;62                     end63                 ram_process:begin64                         da_data_ <= ram_output_data * rom_output_data + da_data_;65                         if (count2 == 0) begin66                             67                         end68                         else begin69                             count2 <= count2 - 16‘d1;70                         end71                         ROM_count <= ROM_count + 5‘d1;72                         state <= ram_read;73                     end74                 state_data_output: begin75                         da_data <= da_data_[31:16] + 16‘d32767;76                         state <= ram_write;77                     end78                 default: state <= ram_idle;79             endcase        80     end    

Improved state machine

This figure shows the improved simulation signal:

During the debugging process over the past few days, many small problems have been encountered, resulting in the simulation results being a little different from what I expected. I found that I had little knowledge of OpenGL, it remains in the C language debugging status.

Convolution design Note 2