Cross-Clock Domain Interface Conversion Circuit

1 module handshake (2 input clka, wra_n, da, clkb, RST, 3 Output Reg [7:0] DB, 4 output Reg wrb_n 5); 6 7 Reg ACK, temp, req1; 8 Reg [7:0] data; 9 always @ (posedge clka or negedge RST) 10 if (! RST) 11 Data <= 8'd0; 12 else if (! Wra_n) 13 Data <= {data [], da}; // data <= {da, data []}; 14 always @ (posedge clkb or negedge RST) 15 if (! RST) 16 begin17 req1 <= 1 'b1; 18 temp <= 1 'b1; 19 end20 else 21 begin22 temp <= wra_n; 23 req1 <= temp; 24 end25 assign wra_n_rising = temp &&(~ Req1); // capture the rising edge of wra_n to enable wrb_n to have a clock cycle of 26 always @ (posedge clkb or negedge RST) 27 if (wra_n_rising) 28 begin29 wrb_n <= 1 'b1; 30 dB <= data; 31 end32 else33 begin34 wrb_n <= 1 'b0; 35 dB <= 8' hxx; 36 end37 endmodule

Requirement: complete two time-domain interface conversion circuits.

Explanation: String Conversion:Data <= {data [], da}; (input starting from D7 and moving left) Data <= {da, data [7]} (input starting from D0, shift right continuously)

　Capture the rising edge of the write signal and convert it to the B-domain enabling signal simultaneously output with the data.

Cross-Clock Domain Interface Conversion Circuit