The SPI is an abbreviation for the Serial Peripheral Interface (Serial peripheral Interface). Motorola has introduced a synchronous serial interface technology, is a high-speed, full-duplex, synchronous communication bus.
The SPI communication principle is very simple, it works in the master-slave mode, which usually has a master device and one or more slave devices, requires at least 4 wires: They are SDI (data input), SDO (data output), SCLK (clock), CS (Chip).
(1) sdo/mosi--main equipment data output, from the device data input;
(2) sdi/miso--main equipment data input, from the device data output;
(3) sclk--clock signal, generated by the main equipment;
(4) cs/ss--from the device to enable the signal, controlled by the main device.
CS is not difficult to understand as a chip selection signal. When multiple slave devices are hung on the bus, the host can select to activate the device by controlling the chip selection signal from the device and complete communication with the device. The general chip is selected as low-power, and is in the selected state.
It should be explained that there are 4 different modes of SPI communication, different slave devices may be configured to a certain mode at the factory, which cannot be changed, but both of our communication must be working in the same mode, so we can configure the SPI mode of our main device, Control the communication mode of our main device via Cpol (clock polarity) and cpha (clock phase), as follows:
Mode0:cpol=0,cpha=0
Mode1:cpol=0,cpha=1
Mode2:cpol=1,cpha=0
Mode3:cpol=1,cpha=1
The clock polarity Cpol is used to configure the level of the SCLK for which state is idle or active, and the clock phase cpha is used to configure the data sample to be on the first few edges.
As a special application of the cryptographic chip, the SPI communication most of the standard SPI interface protocol, but there are no exceptions, the debugging process has a few notes:
1, the encryption chip as a piracy function module or data encryption and decryption module, most of the SPI slave device, the host computer as an SPI.
2, host SPI set to Ckpol=0, Ckpha=0. The meaning: When the idle state, the SCLK is low, the data sampling is on the 1th edge, that is, sclk from low to high level of the jump, so the data sampling is on the rising edge, data transmission is on the falling edge.
3, some encryption chip protocol is special, and because the SPI does not have the synchronous signal function, so the encryption chip needs to use the busy PIN to send a notification signal to the host, when the busy is high, allowing the SPI master device to send data, and vice versa allow the host to receive data.
4, busy for SPI request signal. When busy is low, it allows the SPI master to read the data, and the SPI host side pulls the CS/SS low, SPI_CLK produces the clock.
5, the chip failure can not be normal operation of the reset reset by resetting.
Debugging of SPI Communication in encryption chip
