Deep understanding of the ARM architecture (cloud6410)-cloud6410 storage ing

Reference: http://blog.csdn.net/eagle_lzt/article/details/6310094

Reference: http://www.threeway.cc/sitecn/InformationInfo.aspx? PID = 1637 & tid = 1380

The physical memory of is divided into two parts: memory and pheriperal. The address ranges from 0 to 0 ~ 0x6fffffff and 0x7fffffff ~ 0 xffffffff. The system accesses memory space through the spine bus and pheriperal space through the peri bus. To adapt to the access speed of different peripherals, high-speed peripherals such as LCD, camera, and accelerator are accessed through the AHB Bus, and low-speed peripherals such as IIC and watchdog are accessed through the APB bus.

Memory:

(1) the physical address of the starting image area is 0x00000000 ~ 0x07ffffff, a total of 128 MB, is used to start the system. However, there is no actual storage medium corresponding to this range. You can only select a specific start medium through om [] And then map the physical address of the corresponding medium to this start zone, for example, after the irom startup mode is selected, the address space occupied by irom is mapped to the space starting from 0x00000000. The pilot image area shows an image pointing to a part of the memory or a static storage area. The starting address of the boot image is 0x0000_0000.

 

(2) the physical address of the internal memory zone is 0x08000000 ~ 0x0fffffff, 128 MB in total. This region corresponds to the internal memory address, and the internal ROM and SRAM are distributed in this interval. Where,0x08000000 ~ 0x0bffffff corresponds to the internal ROMOf course, in fact, the internal ROM is not as much as 64 MB, and only 32 KB has the actual storage medium. This 32 KB is a read-only zone and the boot code in irom mode is put, the first code to run when irom is selected is bl0, Which is solidified by the manufacturer.0x0c000000 ~ 0x0fffffff corresponds to internal SRAM, Readable and writable, when Nand
When the flash drive is selected, it can be mapped to the boot image area. .

 

(3) the physical address of the static memory area is 0x0000000 ~ 0x3fffffff, 6*128 MB in total. This area is used to access devices mounted on an external bus, such as SRAM, nor flash, and onenand. This region is divided into six banks, each of which is 128 MB, and the data width can be up to 16 bits. Each bank is determined by xm0cs. Unlike S3C2410, bank2 ~ Bank5 can be mapped to non-linear memory such as NAND Flash and CF ~ The bank5 address segment can directly access the NAND
On the contrary, when mapped to these devices, the address of these banks cannot be used any more. The access to these non-linear memory still needs to be carried out through the AHB Bus of the pheriperal space, the access method is the same as that in S3C2410. However, when xm0cs2 is mapped to NAND Flash, steppingstone's SRAM is mapped to the 4kb starting with bank2, when bank2 was started in NAND flash mode, it was mapped to the place starting from 0x00000000. In fact, it is to map steppingstone to 0x0000000, which is similar to that of S3c2410.

 

(4) the physical address of the dynamic memory zone is 0x40000000 ~ 0x6fffffff, 3*256 MB in total. The first MB is the reserved zone, and the actual dynamic memory zone is 0x50000000 ~ 0x6fffffff is divided into two intervals, accounting for 256 MB respectively. You can select two intervals through xm1cs [0-1] of DMC. This memory Zone mainly refers to the extended dram, which can be up to MB of dram.

2. The pheriperal peripheral area is accessed through the peri bus. Its address range is 0x7000_0000 ~ 0x7fff_ffff. All SFr in this address range can be accessed. And if the data needs to be transmitted from nfcon or cfcon, the data needs to be transmitted through the peri bus.

Special Device address space:

AHB Bus memory ing