Design of communication between SDH Transmission System boards of HDLC Protocol

1 Introduction

Inter-board communication bus is one of the key technologies that determine the stability and reliability of SDH system equipment. The physical layer channels of Inter-board communication cannot be error-free. You must select an appropriate data link layer protocol to overcome faulty channels. The Inter-board communication in the SDH network element is limited by the cost and complexity. Generally, it is recommended to use the serial communication mechanism built in the single-board Mcu system. In the communication interface built in the MCU device, it is common to use traditional UART serial communication interfaces. In theory, the maximum speed of UART asynchronous serial communication is 115200b/s. Therefore, the transmission efficiency is low and it is only suitable for the interconnection of simple information between boards. As the complexity of the board software increases. the bandwidth required to pass through the inter-board communication bus will also increase: as the system becomes more complex, the length of Inter-board communication bus packets is also increasing, inter-board communication data traffic is growing. the requirements for inter-board communication bus transmission are also constantly improved. We plan to study the HDLC protocol for UART speed insufficiency. motormla's MPC852T processor is used. using its support for the HDLC protocol, we try to use the HDLC protocol for inter-board communication to verify its reliability and communication rate improvement.

2 Application of HDLC in SDH Transmission System

HDLC (High level datalinkcontrol Proeedures, Advanced Data Link Control Procedure) is widely used in the field of data communication and is an important technology to ensure reliable data communication. HDLC sends and receives data in a standard format including address, control, information, and CRC (referred to as frame. All frames start with one start sign (0x7E) and end with one end sign (0x7E. Between the start and end signs. One frame contains the address domain (A), control domain (c), O to 5000 bytes of information domain (I) (optional), and the FCS domain. The Frame Structure of HDLC is as follows:

HDLC uses a unique binary series 01111111O (0x7E) to determine the first frame (OpeningFlag) and the last frame (ClosingFlag ). after encoding, other parts between the start and end signs of one frame prevent 5 consecutive "l ".

Address field (A) is used to set the site address for multi-point communication. When receiving A frame, if the address field (A) does not match the site, the frame will not be received. One more thing worth noting is that. FCS domain. Cyclic Redundancy verification (2RC) is used to verify all other domains except the flag. HDI compaction ensures reliable data transmission through the: FCS domain. For more information about HDLC, see references.

SDH system is the main means of transmission in the current telecommunications system. It consists of some SDH network elements for synchronous information transmission, multiplexing and cross-connection over optical fiber. The traditional SDH network element structure 1 is shown in.

In the system shown in figure 1, the NCP unit component of the Network Element control panel is an important part of the SDH system. The performance and alarm information of each function board in the system should be sent to the network management system through this unit. At the same time, some commands of the network management must also pass. NCP is delivered to each Board. In the system, inter-board communication forms a typical multi-host system. The NCP unit is a host in the multi-host communication system. The other components are slave machines.

The communication reliability of the NCP Unit and other components is high, the Information volume is large, and the real-time performance is high. The SDH system's Network Element backplane bus line length is relatively long, so we have to consider electromagnetic interference, signal integrity, impedance matching, Level Selection and other issues. Traditional UART communication is obviously not competent. With the superior performance of HDLC protocol, it can achieve highly reliable and efficient inter-board communication.

Communication Design Between 3SDH Transmission System boards

3.1MPC852T

The MPC85T is an embedded communication processor in the MPC866PowerOUICC series. The core clock speed of the MPC852T can reach MHz. it is integrated with three modules: CPU core (PowerQUICC), System Interface Unit (SIU), and communication processor (CPM, because of its low cost, strong communication capability, and flexible interfaces of multiple communication protocols, it is particularly suitable for communication and network applications. The MPC852TPow-erQUICC is integrated with two processing blocks, one being an Embedded PowerPC core, and the other being a RISC Controller. System diagram 2.

The communication protocol processor (CPM) module is the focus of attention. It facilitates the powerful communication processing capability of the MPC852T. CPM is a RISC processor and has multiple Communication Controllers, including two Serial Communication Controllers (SCC ), supports multiple communication protocols (Ether-net, HDLC, UART, and transparent transmission ). The SCC port is the most distinctive interface. by operating the corresponding registers, independently developing the sending and receiving drivers, or calling the drivers related to the operating system, the SCC port can complete superior inter-board communication functions.

Based on the data provided by the MPC852TDatasheet, the communication rate between HDLC boards supports Nx64kb/s, and the maximum value of N is 64, that is, the theoretical maximum communication rate is 4 Mb/s, the practical rate should be changed depending on CPM utilization and Core processing capability. The theoretical maximum rate of UART is 115.2kb/s. The theoretical comparison result is very obvious.

Design of SCC port for 3.2MPC852T Processor

In terms of hardware design, the HDLC data link layer protocol requires proper physical layer support to achieve high reliability and high traffic. Considering the line length and Communication Rate of the SDH Network Element backplane, the main features of the three common serial communication standards are listed.

From table 1, we can see that the transmission distance and speed of RS 485 can meet the design requirements, and the cost is low and easy to buy, so we select RS 485 to complete the communication system design. 3.

In terms of software programming. First, set the channel parameters of the SCC port. In this design, set SCC3 to HDLC mode. Then, design the driver. First initialize SCC3 and the storage area when the driver is running, and then perform the sending and receiving operations. The initialization process of SCC3 and the storage area is summarized as follows: initialize SDCR to provide priority on the U bus. 1. Set SICR to connect the clock to SCC3 1. Set SCC3 parameter RAM maximum receive cache length 1. Command register (CPCR) write the corresponding command to initialize sending and receiving parameters 1 initialize HDLC parameter RAM, including error counters and frame address domain 1 initialization receiving and sending cache description 1 initialization shielding register to allow the expected event to occur interrupted 1 initialization CIMR to allow the CPM device to generate an interrupt 1 initialization General SCC3 Method register High and Low Level 1 Initialization Protocol definition mode register, including the number of flags, HDLC bus mode. flag sharing allows sending and, or receiving in a low register (GSMR_LX) Setting SCC3 mode.

After initialization, you can enter the sending and receiving status. The receiving process is as follows: when the ENR bit in the GSMR_LX register is allowed, the HDLC controller enters the receiving permitted State. In this state, the Controller waits for one flag. When one flag is displayed, the Controller enters the permitted address State and waits for one non-flag, which must be one address. The controller compares the address with the address in the HADDRX and HMASK fields. After the address match, test the RxBD status mode byte. if the receiving is ready, it starts receiving. One data packet is cached in multiple places. the L-bit of RxBD bytes indicates whether it is the last cache of the received frame. if not, continue receiving; If yes, end receiving after CRC verification. Process 4.

Figure 4: RxBD (Receiver-BufferDescrIPtor, receives the buffer descriptor) is the interface between the Controller and the buffer such as SCC and SMC. The data structure of RxBD is shown in table 2.

Each RxBD manages one BUFFER zone in the memory. RxBD determines the first and last addresses of this BUFFER zone. The data to be received by CPM is placed in this BUFFER zone. Datalength describes the data length. Statusandcon-trol describes the data and the status of the BUFFER zone. The driver sets and reads parameters in RxBD to judge the status of data and BUFFER, and controls data sending and receiving.

Multiple RxBD can be placed continuously in DPRAM or memory to form an RxBD table, so that the CPM controller can receive or send multiple frames of data before the driver intervention. the number of data frames is determined by the number of RxBD tables.

The sending process is similar to the receiving process, which is limited by space and will not be described in detail.

3.3 test results and performance analysis

According to the flow chart, the C language is used for programming and debugging is run on the PSOS operating system. In order to check and test the SCC3 port's packet loss rate and other performance, A sping command is compiled specially to simulate the ping command in TCP/IP, And the SCC3 port is tested with a large packet (1024 bytes) for a long time. the test command is:

Sping sub-shelf number slot number maximum interval of cpu number package size (10 ms)

Test Platform 5. The Board connected with a network cable is an NCP board, and the bottom left is a light board. The microcomputer communicates with the NCP Board through the network cable. After running the telnet command, it is equivalent to the NCP Board itself. The NCP board and the optical Board communicate with each other through the HDLC protocol through the backboard. Then, the performance of the SCC3 port can be tested by executing the sping command. Figure 5 shows the hardware platform used for actual measurement. During the actual measurement, 1024 bytes were used to verify the processing capability of large data packets, and 1000 times were repeated.

The test results show that the packet loss rate of large data packets is zero. From the transmission rate, the average 70 ms time includes the time for sending and receiving, and the one-way time is 35 ms, the actual transfer rate is about 234.1kb/s. Because the test is performed on a normal running board, MCU not only processes HDLC communication. most of the resources are processing other functions, so the actual test results are much slower than the theoretical value. However, from the data size required for communication between the transmission system boards, the actual test results have already met the requirements.

4 Conclusion

In this paper, the HDLC protocol is used to redesign the limitations of UART communication between boards. in addition, the design scheme is implemented using the MPC852T, and the driver program is compiled and debugged on The PSOS operating system. Satisfactory results are obtained. The SDH system equipment has been developed using this method, and the product is stable and reliable. This design method can also be applied to the communication between routers, mobile communication base stations, and receiver devices.