Differences between wire and Reg types in Tilde

Every time you write the code in OpenGL, you will consider setting a variable of the wire or Reg type. Therefore, you have sorted out some information about this on the internet for future search.

Wire indicates pass-through, that is, as long as the input changes, the output immediately and unconditionally reflects; Reg indicates that there must be a trigger before the output will reflect the input.

If this parameter is not specified, the default value is 1-bit wire. Specify the output wire type, which may be multiple bits or make the program readable. Wire can only be assigned consecutively by assign, while Reg can only assign values in initial and always. Wire is used in the continuous value assignment statement, while Reg is used in the process value assignment statement.

In a continuous value assignment statement, the left side of the expression can be updated immediately based on the calculation result on the right side of the expression. In terms of understanding, it is equivalent to directly connecting a line after a logic. This logic corresponds to the right side of the expression, and this line corresponds to wire. In the value assignment statement, the calculation result on the right side of the expression is put into a variable when a certain condition is triggered, and this variable can be declared as Reg type. Depending on the trigger condition, the procedure assignment statement can model different hardware structures: if the condition is the rising or falling edge of the clock, the hardware model is a trigger; if this condition is the high or low level of a signal, the hardware model is a latch. If this condition is a change of any operand on the right of the value assignment statement, the hardware model is a combination logic.

The input port can be driven by wire/Reg, but the input port can only be wire; the output port can be of the wire/REG type, and the output port can only drive wire; if the value of the output port in the process block is Reg type, if the value is outside the process block, it is net type. Use the keyword "inout" to declare a two-way port. The inout port cannot be declared as Reg type and can only be of the wire type. The input and two-way ports cannot be declared as registers.

 

Hardware DescriptionThe language has two purposes: 1, simulation, 2. integration.
for wire and Reg, we also need to consider these two aspects.
******************************* **************************************** * *********
from the perspective of simulation, the HDL language faces the Compiler (such as Modelsim), which is equivalent to the Software concept.
at this time:
wire corresponds to a continuous value assignment, for example, assign
Reg corresponds to a process value assignment, such as always, initial
********************************* **************************************** * *******
from a comprehensive perspective, the HDL language is designed for Integrators (such as DC), and should be considered from the perspective of circuits.
at this time:
1. the variables of the wire type are generally a wire.
2. The reg variable has two conditions in the always block:
(1) the sensitive table after always is in the form of (A or B or C), that is, without the clock edge, integrated or combined logic
(2). The sensitive table after always is in the form of posedge CLK, that is, with edge, generally, the logic is time series logic, which includes the trigger (Flip-flop)
in design, input generally, if you do not know whether the upper-level is register output or combined logic output, it is a wire for the current level, that is, wire type. The output signal is determined by yourself whether it is the register output or the combined logic output. Both the wire and Reg types can be used. However, the overall design of external output (that is, the output of the top-level module) requires register output, which is stable and provides better fan-out capabilities.