Duanxx STM32 Learning: The bit-band operation of Gpio

after the bit-band operation is supported, a single bit can be read and written using normal load/store instructions. In CM3, there are two zones in which a bit band is implemented. One is the lowest 1MB range of the SRAM area , and the second is the minimum 1MB range of the inside and outside zones . The addresses in these two districts, in addition to being used as normal RAM , have their own "bit-band alias area", which expands each bit into a 32-bit word with the alias area. When you access these words through the bit-band alias area, you can achieve the purpose of accessing the original bits .

There are a lot of blog notes about bit-band operations, where the code is mostly posted and detailed comments are made

/** ****************************************************************************** * @file GPIO.h * @author Duanx X * @version V1.1 * @data 2015-06-07 * @brief This header file is a supplement to "stm32f10x_gpio.h" * Mainly for the cortex-m3 authoritative guide (Chinese version) CHP05 Memory System--one implementation of the bit band operation * This feature enables the STM32 to act as a bitwise operation on the IO port as a 511-sample * ************************************* */#ifndef _gpio_h_#define _gpio_h_#include "Stm32f10x_gpio.h"/** * The implementation here is from "Cortex-m3 authoritative Guide (Chinese version)" Chp05 memory system, with the operation of the 92nd page directly copied * The purpose is to simplify the bit-band operation, and define a number of dedicated macro *////< the "bit with address + bit number" into the alias address of the macro-# Bitband (addr, Bitnum) ((Addr & 0xf0000000) +0x2000000+ ((addr &0xfffff) <<5) + (bitnum<<2))///<   Convert the address into a pointer to the macro # define MEM_ADDR (ADDR) * ((volatile unsigned long *) (ADDR))///< The bitwise operation of the address # define BIT_ADDR (ADDR, Bitnum) Mem_addr (Bitband (ADDR, bitnum))/** * Below is the address of the GPIO input/output data register * Here the address is according to the stm32f10x refernce manual (RM0008 English) in the * C HP3 Memory and bus architecture 3.2 Memory organization and * CHP9 general-purpose and alternate-function I/Os (GPIOs and Afios), 9.5 GPIO and AFI O Register Maps * The *////< of the Gpio address assignment table is offset 0x8 at the base of the Gpio, which is the address of the GPIOX_IDR, that is, the GPIO input data register #define GPI    OA_IDR_ADDR (gpioa_base+8)//0x40010808 #define GPIOB_IDR_ADDR (gpiob_base+8)//0X40010C08 #define GPIOC_IDR_ADDR (gpioc_base+8)//0x40011008 #define GPIOD_IDR_ADDR (gpiod_base+8)//0x40011408 #define GPIOE_IDR_ADDR (GPIOE_BASE+8  )//0x40011808 #define GPIOF_IDR_ADDR (gpiof_base+8)//0x40011a08 #define GPIOG_IDR_ADDR (gpiog_base+8)//0x40011E08 < offset 0x8 on the base address of the Gpio, that is, the GPIOX_ODR addresses, that is, the GPIO output data register #define GPIOA_ODR_ADDR (gpioa_base+12)//0x4 001080C #define GPIOB_ODR_ADDR (gpiob_base+12)//0x40010c0c #define GPIOC_ODR_ADDR (gpioc_base+12)//0x4001100c #def Ine gpiod_odr_addr (gpiod_base+12)//0x4001140c #define GPIOE_ODR_ADDR (gpioe_base+12)//0x4001180c #define GPIOF_OD R_ADDR (GPIOF_BASE+12) 0X40011A0C #define GPIOG_ODR_ADDR (gpiog_base+12)//0x40011e0c/** * The following is a further macro definition based on the use of the Gpio for the bit band operation * Its use method as               * If the GPIO is output mode: * STEP1: The GPIO is initialized to output, for example: Gpio_inittypedef duanxx_gpio_initstructure;                    < enable GPIOA, Rcc_apb2periph_gpioa Rcc_apb2periphclockcmd (Rcc_apb2periph_gpioa, enable);        < Configure and pa.1 as output push-pull duanxx_gpio_initstructure.gpio_pin = gpio_pin_1;        Duanxx_gpio_initstructure.gpio_speed = Gpio_speed_50mhz;        Duanxx_gpio_initstructure.gpio_mode = gpio_mode_out_pp;            Gpio_init (Gpioa, &duanxx_gpio_initstructure); *STEP2: Control PA1 output paout (1) = 0; &LT;PA1 output Low Level paout (1) = 1;  &LT;PA1 output is high * Of course, we can also use the macro definition, the following macro definition for further encapsulation * This will be more conducive to the use of meaningful gpio control * such as PA1 link is led, then you can have the following actions #define                LED Paout (1)///<led for PA1 #define LED_ON 1///< defines the LED light value #define LED_OFF 0///< defines the value of the LED off LED = Led_off; /< led off LED = Led_off;    < LED light, ********************************************************************** * Similar operation for GPIO input        * The first step is also initialization, the GPIO initialization bit input * The second step is to read the GPIO, such as * to determine if the PA1 is high level as follows: if (PAin (1) = = 1) {.... } **/#define PAOUT (n) bit_addr (gpioa_odr_addr,n) #define PAIN (n) bit_addr (gpioa_idr_addr,n) #define PBOUT (n) B IT_ADDR (gpiob_odr_addr,n) #define PBIN (n) bit_addr (gpiob_idr_addr,n) #define PCOUT (n) bit_addr (gpioc_odr_addr,n) #de Fine Pcin (n) bit_addr (gpioc_idr_addr,n) #define PDOUT (n) bit_addr (gpiod_odr_addr,n) #define PDIN (n) bit_addr (GPIO    D_idr_addr,n) #define PEOUT (n) bit_addr (gpioe_odr_addr,n) #define Pein (n) bit_addr (gpioe_idr_addr,n) #define PFOUT (N) BIT_ADDR (gpiof_odr_addr,n) #define PFIN (n) bit_addr (gpiof_idr_addr,n) #define PGOUT (n) bit_addr (gpiog_odr_addr,n) #define PGIN (N) bit_addr (gpiog_idr_addr,n) void Gpio_disale_jtag (void); #endif

Duanxx STM32 Learning: The bit-band operation of Gpio