[Embedded development] Introduction to ARM chips (ARM chip type | operating mode of ARM processors | ARM registers | ARM addressing ),

[Embedded development] Introduction to ARM chips (ARM chip type | operating mode of ARM processors | ARM registers | ARM addressing ),

Author: Han shuliang

Blog: http://blog.csdn.net/shulianghan/article/details/42375701

Download related resources:

-- Samsung ARM Architecture Reference Manual documentation: http://download.csdn.net/detail/han1202012/8324641

I. ARM chip type

1. ARM Classification

(1) ARM classification Type (chip | core | instruction Architecture)

ARM Classification:

--ARM chip type: 6410,244 0, 210;

--ARM core type: Arm11, arm9, CortexA9;

--Command Architecture: Armv7, armv6;

(2) Relationship between ARM chips and ARM Cores

Relationship between chips and cores: Chip contains core;

--2440 chips: Including the arm9-core;

--6410 chips: Contains arm11 cores;

--210 chips: Contains the CortexA8 core;

(3) Relationship between ARM core and command Architecture

Relationship between ARM core and command Architecture:

--ARM9.: Armv4 command architecture;

--ARM11: Armv6 command architecture;

--CortextA8: Armv7 command architecture;

2. ARM Evolution

(1) Classic camp

Development History: ARM11: the highest performance of ARM11 and the lowest performance of arm7;

(2) Cortex camp

Cortext Series:

--Cortex-M series: No operating system, applicable to industrial control, similar to single-chip microcomputer;

--Cortex-R series: For real-time applications, with emphasis on real-time performance, operating systems can be run;

--Cortex-A Series: Mainly for multimedia applications. Currently, most smartphones belong to this series;

Performance recurrence: Cortex-M0 --> Cortex-M1 --> Cortex-M3 --> Cortex-M4 --> Cortex-R4 --> Cortex-A5 --> Cortex-A8 --> Cortex-A9;

(3) Comparison between Cortex and ARM

Comparison between ARM and Cortext:

--ARM7: ARM 7 and Cortext-M3 similar, there is no operating system, performance Cortex-M3 slightly higher, but high Limited;

--Arm9and ARM11: Arm9and ARM11 and Cortex-R4 performance is similar, ARM11 is not as good as Cortex-A5, far less than Cortex-A8 and Cortex-A9;

3. Chip performance comparison (processing speed | cache | memory interface | OS)

(1) processing speed comparison

Chip processing speed comparison: Find Clock & Power Management in the corresponding chip manual to view Clock-related parameters;

--6410: 533 MHz ~ 667 MHz;

--2440: 12 MHz crystal oscillator corresponding to 405 ~ 532 MHz processing speed;

--210: 800 MHz ~ 1 GHz;

(2) cache comparison

Chip cache comparison: Chip manual for chip removal;

--6410: 16 K Command cache and 16 K data cache;

--2440: 16 K Command cache and 16 K data cache;

--210: 32 KB Instruction Cache and 32 KB data cache;

(3) memory interface comparison

Chip memory interface comparison: The SDRAM has been eliminated;

--2440: Provides the SDRAM memory interface;

--6410: SDRAM and DDR memory interfaces are provided;

--210: Provides DDR1 and DDR2 memory interfaces;

(4) supported Operating Systems

Comparison of operating systems supported by chips: Find the corresponding chip in the chip manual;

--6410: WinCE | Linux | Android;

--2440: WinCE | Linux;

--210: WinCE | Linux | Android;

(5) Other Commercial Information

Chip business comparison:

--6410: Continue to use;

--2440: Samsung announces shutdown;

--210: Continue to use;

Ii. ARM Working Mode

Corresponding Manual:ARM Architecture Reference Manual.pdfManual, which can be downloaded in this blog;

--Unit content: Programmers 'model, A2.2 Page 41;

--Manual: Http://download.csdn.net/detail/han1202012/8324641

1. processor working mode

(1) Example of ARM working mode

Working Mode Diagram: The image is taken from the ARM Architecture Reference Manual.pdf manual, Page 41, and A2.2;

(2) Introduction to ARM working modes

Work mode Introduction:

--User Mode (usr): Normal application running mode;

--FIQ mode (fiq): Fast interrupt mode;

--IRQ mode (irq): Normal interrupt mode;

--Supervisor mode (svc): Protection mode provided for the operating system;

--Abort mode (abt): Abnormal mode caused by access to virtual memory;

--Undefined mode (und): The command mode is not defined;

--System Mode (sys): This mode is available for armv4 and later versions;

Linux Operating Mode: The system runs in usr mode and the kernel runs in svc mode;

Iii. ARM registers

Corresponding Manual:ARM Architecture Reference Manual.pdfManual, which can be downloaded in this blog;

--Unit content: Programmers 'model, A2.3 Page 42;

--Manual: Http://download.csdn.net/detail/han1202012/8324641

1. Register Introduction

Register Introduction:

--Number of registers: ARM has 37 registers;

--General registers: 31 General registers. The program counter is also a general register;

--Status Register: 6 Status Registers;

--Illustration:

--Register illustration: From Page 43;

2. General registers

(1) General Register Classification

General Register Classification:

--Non-grouping register: R0 ~ R7;

--Group Register: R8 ~ R14. The registers used in different modes are different;

--Program counters: PC pointer, Which is R15;

(2) common general register Parsing

R13 register: Usually used for SP Stack pointer;

R14 register: Used as a link register;

--Role 1: Save the return address of the function;

--Role 2: When an exception occurs, it is mainly used to record the return address of the function;

R15 register: PC pointer, program counter;

3. Status Register

(1) Reasons for status registers in various modes

Status Register:

--Illustration:

--Status Registers corresponding to each mode: When an interrupt occurs, run the interrupt program and save the corresponding cprs to the SPRS_xxx register in the corresponding mode. For example, if the current session is interrupted in scv mode, save the Status Register to the SPSR_svc register, after the interrupt is executed, write the status from SPSR_svc back to the CPRS register;

(2) CPSR register bit Introduction

CRSR register Introduction:

--Illustration:

--N-bit: Compare two numbers a and B, that is, perform subtraction (a-B). If a <B, the subtraction result is negative, N = 1; if a> = B, the subtraction result is positive or 0, N = 0;

--Z-bit: Compare two numbers. If only two numbers are equal, Z = 1;

--I-bit: I = 1 cannot interrupt;

--F-bit: When F = 1, fast interruption is not allowed;

--M-bit: Accounts for 5 digits 0 ~ 4. It is mainly used to indicate the processor mode. It can be read and set, for example:

Iv. ARM addressing

Corresponding Manual:ARM Architecture Reference Manual.pdfManual, which can be downloaded in this blog;

--Unit content: Programmers 'model, A2.3 Page 42;

--Manual: Http://download.csdn.net/detail/han1202012/8324641

Addressing Mode: ProcessorLocate the instruction operand Based on the instruction information;

1. Immediate addressing

Overview:

--Addressing Process: The operand itself is given in the instruction, and the retrieved instruction can also obtain the operand;

--Operands: The operand retrieved from the command is the immediate number;

--Addressing Mode: This method of extracting the immediate number from the command is immediate number addressing;

Immediate addressing example:

--Example: ADD R0, R0, # 0x3F;

--Analysis: Add R0 + # 0x3F and add the result to R0;

Immediate addressing requirements: The second source operation number "#" is the suffix;

2. Register addressing

Introduction to register addressing: The value in the register is used as the operand;

--Example: ADD R0, R1, R2;

--Example: Add the numbers in the R1 and R2 registers and store the results in R0;

3. Register indirect addressing

Introduction to register indirect addressing: The number of operations in the register is in the memory, and the address where the register stores the memory;

--Example: LDR R0, [R2];

--ExampleThe memory address of the operands is stored in register R2, And the operands are retrieved from the memory and saved to R0;

4. base address addressing

Introduction to base address change addressing:

--Base Address Register: Stores a base address in the register;

--Offset: An offset is given in the instruction, and the base register is placed in a bracket number;

--Example: LDR R0, [R1. #4];

--Example: Extract the address from R1, add 4 to the address, and retrieve the data from the added address;

5. Relative addressing

Introduction to relative addressing: The current value of the PC pointer is the base address. The address label in the instruction is the offset, and the two are the valid addresses;

--Example: Bl next will jump to NEXT for execution. After execution, it will return to the original program;

Bl next; jump to NEXT and execute

......

NEXT

......

Mov pc, LR; returned from subroutine

Author: Han shuliang

Blog: http://blog.csdn.net/shulianghan/article/details/42375701

Download related resources:

-- Samsung ARM Architecture Reference Manual documentation: http://download.csdn.net/detail/han1202012/8324641