Error detection for specific timing rules

document content: for a specific timing transmission protocol, at the receiving end of its detection and judgment, transfer the correct storage otherwise discarded.

First, protocol Information

The protocol sequence diagram is as follows:

The corresponding agreement provides as follows:

A: During the CS low-active period, the source sends data on the CLK rising edge, and the beacon receives data on the falling edge of CLK, and the continuous two bytes CLK maintains a low of at least 2 CLK cycles;

B: Two consecutive chip selection signal is valid, the selection of invalid high-level retention time is greater than 10 CLK cycles;

C:CLK signal clock frequency is 2.5MHz;

D: In the CS low effective period, the source continuously sends the data size to be 188byte;

E: The first byte should be 0x47.

Design ideas: According to the above provisions to set a number of conditions, conditions to meet the string and transformed after the parallel data into RAM, otherwise discarded, which can be achieved by the enable signal on the RAM. It also uses two RAM to implement a ping-pong operation that can still be stored while reading.

Second, Module Design

From the above protocol information analysis can be, in the design of the project need to do a few modules:

A: edge detection, processing time need to detect CS and CLK up and down the rise along the corresponding processing;

B: string and transform the module, because the output is serial data, and the detection of storage is 8bit processing;

C: The detection of the head byte, need for 0x47;

D: clock cycle detection, requires 8 consecutive CLK and adjacent to a byte to be spaced at least 2 clk;

E: The number of bytes of detection, requires 188 byte.

1. Edge Detection

The output of the CS signal CLK signal edge detection, statistics CLK edge implementation of the cycle of statistics and then to achieve a certain value of the time processing, such as can be used to indicate the end of 1 byte transmission.

Edge detection can be done by storing the input signal for a period and then outputting the inverse with the latest cycle of the data to be detected on the rising and falling edges. The corresponding RTL diagram is as follows:

As can be seen from two graphs, one is the D flip-flop and output data to want with, one is the D trigger and the input signal to think with. So how do you achieve the detection of rising and falling edges through such operations?

The work flow is as follows:

(1) d trigger through the clock CLK trigger, output signal_i signal, save the t0 moment signal;

(2) At the same time signal_i signal through and non-gate output signal, retains the current moment T1 trigger signal;

(3) corresponding to the above two diagram, after the output signal with the gate divided into two cases, as follows:

A) Only the t0 time is low, and the T1 time is high, and the gate output is high, this is the rising edge;

B) Only the T0 time is high, and the T1 time is low, and the gate output is high, this is the falling edge.

The program looks like this:

The det_posedge_en can be used to select the rising or falling edge, and the corresponding edge detection for CS and CLK is as follows:

The Edge detection module generates three variables for the processing of other modules, the variable Clk_pdge&clk_ndge&cs_ndge

2 , string and transform modules

string-and-transform through the statistics of the CLK cycle, and the serial data into a parallel variable, in the statistics to 8 CLK cycles, that is, a byte transfer end, the event of the serial variable output, that is the first byte string and transform the result.

At the same time, the serial variable should be set to 0 when CS is low, and a serial data is entered into the parallel variable at the CLK rising edge.

The statistics section and parallel storage variables are as follows:

From the program can be seen each produced a CLK rising edge, the CNT plus 1, each input data, it is assigned to the parallel variable P_reg. After the assignment is the time to get the problem, we also need to generate a parallel clock to drive parallel data, the program is as follows:

It can be seen in the program that the data in the parallel variable P_reg is assigned to data_p for output and a parallel clock clk_p is generated when CNT is 7, resulting in 8 rising edges.

3 , head byte detection

3, 4, 5 these three modules are to determine whether the frame being transmitted is valid, whether the frame needs to be stored in RAM, three modules generate a signal, and eventually assigned to the RAM signal to the write enable end.

Head byte detection, there are two points to be detected, one is the first byte, and whether it is 0x47. So like the 2nd, one is the statistic of the period, and the other is the serial data string and changes to see if the first byte is 0x47. The corresponding program is as follows:

With conditional statistics, the next step is to judge the conditions as follows:

The program can be seen, when two conditions are satisfied, the condition Premble_enable_reg 1, that is, the first byte of 0x47 this condition has been satisfied. Another problem is that we need to output this enable variable because it needs to remain valid for the next 188byte, so that you can continuously read a frame of data that has been stored. The Premble_enable_reg can be assigned to the final enable signal premble_enable by the end of a frame transfer at the rising edge of CS, so that the read enable can be effective when the next frame satisfies the readable condition.

4 , clock cycle detection

Clock cycle detection is primarily used to detect a uniform 8 CLK cycles within a byte, with a minimum of two clk cycles between adjacent bytes. The CLK period is known as a condition of 2.5MHz, and we use the 50MHZ system clock to sample it. The system clock is 20 times times the CLK, so when you count the CLK and the system clock Clk-sys, you can determine whether a byte is transmitted through a continuous 8 CLK by comparing the count period, and you can also detect whether the adjacent byte is more than 2 CLK apart.

The first statistics for two clocks are as follows:

CNT at the start of the next byte clear 0,cnt_sys 0 after a byte transfer is complete. Below you need to determine whether there are 8 clk in the 8*20=160 Clk_sys cycle, the procedure is as follows:

The second half of the last 1 clk periods (i.e., the value of Cnt_sys between 149 and 159) in the specified 8 CLK time contains 8 CLK, which indicates that 1 bytes contain a uniform 8 CLK. At this point the Clk_enable_reg_8 is 1. We found that as long as each byte is evenly transmitted, the clk_enable_reg_8 is always 1, so as long as the error is generated, Clk_enable_reg_8 will set 0, which produces a falling edge.

Determine that the interval between two bytes is at least greater than 2 CLK, you can use the Clk_sys statistics valid byte plus byte interval for this long period, still only includes 8 CLK cycles. The procedure is as follows:

The above 149 plus at least two CLK cycles, or 40 clk_sys, 189 Clk_sys cycles still contain only 8 CLK, then the CLK_ENABLE_REG_10 is 1. Same as the clk_enable_reg_8 of a variable, Whenever an error occurs, a falling edge is generated.

Edge detection of the above two variables is as follows:

Generate variables Clk_enable_reg_8_ndge and Clk_enable_reg_10_ndge. By judging whether these two variables are generated, to assign a value to the Enable signal, as follows:

is available in the program, when no falling edge is generated, the enable signal remains at 1, which is effective. Finally, this variable will be transferred to the final enable signal clk_timing_enable when the rising edge of CS is 188byte. As follows:

5 , byte count detection

The detection of the number of bytes in 4 parts of the existing situation, only to detect the CLK period is 8*188, all the programs are as follows:

When containing 8*188 CLK, enable signal byte188_enable 1.

6 , data storage and effective information reading

After the processing of the above-mentioned subsections, a plurality of enabling signals, such as premble_enable, clk_timing_enable, byte188_enable, etc., are combined to form the control enable of read/write RAM.

The data entered in this section is the parallel data and the parallel clock after the string and transform, and the data is stored and read on the rising edge of the clock. Therefore, the first step is to detect the rising edge of the parallel clock signal as follows:

Storage section, with two ram for ping-pong operations, when one reads, the other writes. As follows:

Through the RAM write enable signal and Address line control to read and write operation, in each CS for a low cycle has a ram in the write, and whether the read signal needs to be based on the previous description of the three signal is valid to judge, effectively indicate that the data did not occur transmission error, is correct can be read, otherwise do not read.

The first thing to do is to count CS as low cycle:

Then the ram reads and writes according to Cnt_cs.

Reset when reset signal is active first

The rising edge of the parallel clock clk_p triggers the operation, first the CS first cycle. At this time write operation to RAM1, write enable 1, address line increase, the input signal data_p assigned to din_1. RAM2 According to the previous three conditions, if all meet that is 1 o'clock, to RAM2 read operation, write enable 0, that is, read, add the address line, the input signal is 0, the output of the RAM2 dout_2 assigned to the module data output ram_out. When the three enabling conditions are not satisfied, the RAM2 is not read.

Similarly, when CS is 1, the above operation is the opposite, that is, read to RAM1, write to RAM2.

7 , synchronous processing

In fact, before doing many of the above operations, the first need to do a synchronous processing, because the interface clock CLK is provided externally, the system clock Clk_sys and CLK is not synchronous, need to be synchronized, with D trigger implementation. The CS, CLK, and data are processed as follows:

Third, Engineering Overall RTL Figure

The above modules are connected as follows:

Error detection for specific timing rules