Estimation of Chip area

IO neck and core neck are generally referred to as IO Limited and core Limited,
IO Limited: The size of the chip is limited by the number of Io (too many) and has to be done so much. The core part doesn't really work that big. The area calculation is then simplified to calculate the number of IO per side.
Core Limited: Chip area is the core part of the decision, IO not so much
in the case of Core Limited, die size is estimated as follows:
Chip area = Core area + Power Ring area +pad Ring Area
Core area = Ram Area + other macro area + standard cell area
Ram area = RAM itself area + RAM Power Ring area + keepout area  + mbist area
RAM itself area can be Memory compiler or datasheet get,
Some ram can not power ring. If you want, follow the width of power mesh x Ram's length width x 2 = Area
Keepout + mbist area is generally ram itself area of 10%
Other macro area, such as PLL,ADC,DAC, directly add up the area, and then stay % of the Keepout area is good.
The area of the standard cell = (estimated gate count x area per gate)/utilization

Utilization relates to the number of metal layers used and the purpose of the design, and simply calculates the method: ( Personally, this is only an empirical value, for reference only.) –IEEE)
5-storey metal:50%
6-storey metal:60%
7-storey metal:70%
8-storey metal:80%
The above does not include the power dedicated metal layer
If the design is a multimedia chip, generally can increase 3~5% utilizaion, if it is a network chip, you have to reduce 3~5%

Estimation of Chip area