Finite state machine model

The 4th style Verilog HDL model represents the same finite state. In this model, we use the Always statement along the trigger and the level-sensitive always statement to describe the trigger part and the combinational logic part of the state machine separately into two parts.

Note: The use of concurrent (non-blocking) assignment along the trigger's always statement, and the way the blocking assignment is used in level-sensitive always statements;
Example 4.4: Finite state machine Model 4.

Module FSM (Clock, Reset, A, F, G); Module declaration
Input Clock, Reset, A;
Output f,g;
reg [1:0] state, nextstate;

      parameter                                       //Status declaration
            idle  = 2 ' b00,  Start = 2 ' b01, 
            Stop = 2 ' B10, Clear = 2 ' B11;

Always @ (Posedge Clock)
if (! Reset) begin
State <= Idle; Default state
End
Else
State <= Nextstate; State transitions

Always @ (state or A) begin
f=0;
g=0;
if (state = = Idle) begin//In Idel, a judgment
if (A)
Nextstate = Start; Start state
Else
Nextstate = Idle; Keep the Idel state
g=1;
End
else if (state = = start)//in Start, yes! a judgment
if (! A
Nextstate = Stop; Stop State
Else
Nextstate = Start; Keep the start state
else if (state = = stop)//In stop status, a is judged
if (A)
Nextstate = Clear; Clear status
Else
Nextstate = Stop; Keep the Stop state
else if (state = = Clear) begin//is in clear, yes! a judgment
if (! A
Nextstate = Idle; Idel Status
Else
Nextstate = Clear; Keep the clear state
f=1;
End
Else
Nextstate= Idle; Default state
End
Endmodule

Finite state machine model