Parameter passing when Verilog is instantiated

When calling DesignWare, there will usually be a Dw01_add # (a_width,bwidth) syntax, when it is doubtful why, and now it is the source of the search. Doubt whether their basic skills are not solid enough. The usage is as follows  1, Module_name # (Parameter1, Parameter2) inst_name (Port_map), 2, Module_name # (Parameter_name Value),. Parameter_name (Para_value)) Inst_name (port map), the # method is the same as the port map, module multiplier (A, B, product);  & nbsp       Parameter a_width = 8, B_width = 8;          Localparam product_width = A_wi dth+b_width;          input [a_width-1:0] a;          input [b_width-1:0 ] b;          output[product_width-1:0]product;             ge nerate                 if ((A_width < 8) | | (B_width < 8))                      cla_multiplier # (A_width, B_width) U1 (A, B, p roduct);                &NBSP;ELSE&NBsp                     Wallace_multiplier # (A_width, B_width)  u1 (A, B, product);             endgenerateendmodule  This usage is really practical. If there is a module that is often called, this method can make the Verilog level much leaner.  

Parameter passing when Verilog is instantiated