FPGA Implementation of SATA host protocol 1

After three months of hard work and preparation in middle February, another project, FPGA-based SSD read/write control circuit, has been basically implemented. Due to the lack of practical materials and the challenging nature of the project, this process is full of hardships. I hope to write down some experiences for the reference of those who wish to take less detours. Because this project is relatively large, it is not clear in a few words. Maybe I will use five to six articles to talk about this, and it will take a long time to write code articles, I hope to see the patience of the audience first. At the same time, because the complete SATA protocol is a bit huge, my understanding is not perfect, and there are some inconveniences in the middle, I also hope to pass by and point out.

To put it bluntly, here we will first popularize two basic knowledge of hard disks: one is about the storage media of hard disks, and the other is about the interface technology of hard disks. First, let's talk about this storage medium. There are two mainstream hard disk storage media on the market, one of which is the most commonly used CD for mobile hard disks, another is the flash storage media used by the emerging SSD. The specific details of these two types of media are not investigated here. It just briefly describes the advantages of SSD: fast speed, light, and low sound. The disadvantage is that it is expensive and the read/write count is limited. Next, let's talk about this interface technology. Currently, the mainstream hard disk interface technologies on the market include SATA, SAS, and a longer-term ide. What we most often come into contact with is Sata. Sata is developed by IDE, which breaks through many limits of IDE, such as speed and anti-interference. For the hard disk host controller, we are concerned with the interface protocol, and the storage media can be placed in a secondary location.

In the early stage of project development, you must study the relevant materials, including the SATA protocol documents and ATA Protocol documents. Here is a download link, which contains relevant information, including the original documents of the sata3.0 protocol and some useful papers and Chinese documents. You can download them if necessary. Http://download.csdn.net/detail/dianshe12345/7571557. In addition, to use stratixiv devices, you also need to refer to the device manual of stratixiv. You can download the device manual from the official website of Altera, either in English or in Chinese. Of course, if you are using other devices, go to the relevant device manual. It seems that the EP4 GX sequence of Altera also has a high-speed transceiver, but it seems that only sata1.0 transmission rate can be achieved. If you use Altera's device as the SATA protocol, there are two documents that we recommend you to look at, one is "Understanding the SATA-SAS 40nm FPGA solution ", another article is "Implementing SATA and SAS protocols in Altera devices ". These two documents tell us how to use the devices of Altera to implement the SATA Protocol, especially the second one. You can search for them online.

The following describes the SATA protocol. The SATA protocol currently has three versions: sata1.0, sata2.0, and sata3.0. The biggest difference between the three versions is the transmission rate, which is 1.5 Gbps, 6.0 Gbps, and Gbps respectively. The SATA physical interface consists of a 7-pin signal line and a 15-pin power line. The 7-pin signal line consists of three ground lines, two differential input lines, and two differential output lines. SATA data transmission uses analog serial differential signals, which fundamentally changes the problem of inter-code crosstalk in the IDE hard disk. This is also because, when FPGA is used for the SATA protocol, we must choose the chips with dedicated physical devices-high SATA protocol transmission rate, in addition, the digital signal must be converted to analog differential signal transmission. Generally, low-end FPGA chips are not competent, currently, some high-end FPGA chips use internal high-speed transceiver hardware integration to solve this problem, such as the altgx transceiver of Altera and the rocketio Mgt of Xilinx, this is also the reason why the FPGA chip stratixiv needs to be used. I am using the de4 Development Board.

The SATA protocol consists of the physical layer, link layer, transmission layer, and application layer. The application layer provides register interfaces and resolves all ata commands to update registers. The transport layer is located between the link layer and the application layer, which processes control information, the data to be exchanged between the host and the device is encapsulated into a data frame, that is, the frame information structure (frame information structure). The link layer controls the transmission control primitives and data, extract data from data frames and perform 8B/10B encoding/decoding. At the same time, in order to ensure reliable data transmission, the link layer also introduces the CRC-32 verification method, and the data is unbound; the physical layer is responsible for device identification and initialization, to achieve high-speed serial data link, sends and receives encoded serial data streams on the transmission line, concatenates and/or converts the data, and isolates the clock information from the data streams. The following articles will explain the implementation process of the entire project from the implementation of these protocol layers.