FPGA learning notes (2) Module Establishment and variable connection

The projects written by using the OpenGL are connected by one module. Each file represents a module. The module name and file name must be consistent. The basic declaration method of a module is as follows:

//FileName:main_modulemodule main_module(    CLK, RSTn, IO_In, IO_Out);    input CLK;    input RSTn;    input IO_In;    output IO_Out;endmodule

For top-level files, all declared input and output variables can be allocated with pins. The so-called input and output are relative to themselves. If you want to use this variable to read the content, it is declared as input. If you want to use this variable to output the content, it is declared as output.

To capture the CLK, rstn, and io_in of the top-level file and output io_out after processing, you need to create another module (File) as follows:

//File_Name:io_changermodule io_changer(    myCLK, myRSTn, myIO_In, myIO_Out;);    input myCLK;    input myRSTn;    input myIO_In;    output myIO_Out;endmodule

To connect these two modules, that is, to connect the top-level main_module to io_changer, you need to make the following declaration in the top-level file:

wire Out_Receiver;io_changer U1(    .myCLK( CLK ),    .myRSTn( RSTn ),    .myIO_In( IO_In ),    .myIO_Out( Out_Receiver ));

Since the first three variables are declared as input, the top three variables are passed in, and the fourth variable is declared as output, therefore, the value of myio_out in io_changer is passed into the wire variable out_receiver at the top layer. This is similar to the class assignment in C ++. there is a this pointer in front, in the io_changer class, this. myclk is the myclk variable of io_changer. brackets are a method for assigning values. Of course, the output function is also added here.

After two modules are created and compiled, the file connection is automatically completed, and io_changer is used as the sub-file of main_module.

In the module io_changer, to change the value of myio_out, the assign value is generally used.

In the always loop structure, the reg variable is generally used instead of the wire variable. Assume that there is a counter whose value ranges from 0 to 50000000 representing 1 second, so that io_out is flipped once every Ms, you need to write as follows:

reg rIO_Out;always @ (posedge myCLK or negedge myRSTn)        if (!myRSTn)            rIO_Out = 1‘b0;        else if(Counter >= 2500_0000)            rIO_Out = 1‘b1;        else            rIO_Out = 1‘b0;assign myIO_Out = rIO_Out

In order to pass the changes back to the top layer, you also need to assign the out_cycler received to the io_out pin in the top layer, as shown below:

assign IO_Out = Out_Receiver;

FPGA learning notes (2) Module Establishment and variable connection