Freescale mc9s08aw60 Compilation Study notes (vi)

Delay, the assembly often used in the function, that is, the MCU do nothing, just delay for a while. The MCU itself has timers, counters, for the implementation of the delay of course, but a programmer naturally want to achieve more easy to control the function, we use code, program to achieve delay, that is, the use of software delay. The concrete method is: through a, h:x increase and decrease instruction, empty operation instruction NOP and BRN and the corresponding transfer instruction, then uses the circulation structure to realize the delay function. Since it is time delay, you can know how long delay is the best, we know is: MCU bus clock frequency is 4MHz, so a bus cycle takes up time of 0.25us, so as long as the knowledge of the bus cycle of each instruction can calculate how long our program has been running. The realization of delay nature is also the case, these of course to use the knowledge of mathematics, rest assured that the use of calculus, as long as the patience of a bit of accurate calculation of the time delay is not difficult.

Example: Design a delay 10ms delay subroutine, known MCU bus clock frequency is 4MHz.

Analysis: Due to the bus clock frequency is 4MHz, so a bus cycle takes time to 0.25us,10ms delay need to perform equivalent to 40,000 bus cycle instructions. We can first design a sub-program re_cycle that implements a smaller delay, and then call the subroutine multiple times to achieve a longer delay. The code is as follows:

ORG $0070
Num ds.b 1
Count1 ds.b 1

ORG $1860
Re_cycle: 4+7*70+6=500t=125us
mov #70T, num; 4T
DBNZ num,*; 7T
RTS; 6T
DELAY_10MS:; [4+78* (5+7+500)]+4+7*7+6=39999t
mov #78T, count1; 4T
Re_call:
BSR re_cycle; 5T
DBNZ Count1,re_call; 7T
mov #07T, count1; 4T
DBNZ count1,*; 7T
RTS; 6T

Main
BSR delay_10ms; 5~6t
Again
Nop
JMP again


ORG $fffe
DC.W Main

Each instruction takes the time to be marked out, the need is delicate design and accurate calculation, such as the design of the Re_cycle subroutine three instructions just 500T, here to explain the DBNZ this instruction, it is implemented by the function of the previous variable in the number of 1 and 0 comparison, Unequal to the subsequent address and execute, equal to the end of the instruction (that is, minus 1 is not 0 transfer instructions). Here is sure to ask * what it stands for, it represents the address of the instruction itself, DBNZ num,* instruction can be interpreted as NUM decrement 1 is not equal to 0 back to execute the statement, know that num 1 equals 0 after the end. As the note shows, the total elapsed time for the Delay_10ms subroutine to execute is 39999T, plus the call to the Delay_10ms subroutine in main main program takes up 5~6t, so that delay_10ms is not called once, it can be implemented 40004~ 40,005 bus cycles of approximately 10ms delay. Of course, if the design is good enough, it can be more accurate, the closer the 40,000 t the better.

The above implementation of the delay of 10ms, that if the implementation of 100MS,500MS,1MS,0.1MS, the same approach, all rely on sophisticated design and accurate calculation. The following sub-programs are given for delay 1ms and 500ms:

ORG $0070
Num ds.b 1
Count1 ds.b 1
Count2 ds.b 1

ORG $1860
Re_cycle: 4+7*70+6=500t=125us
mov #70T, num
DBNZ num,*
Rts

DELAY_1MS:; [4+ (5+7+500) *8+6]=4106t
mov #08t, Count
Re_call:
BSR Re_cycle
DBNZ Count,re_call
Rts

DELAY_10MS: 39999T
mov #78T, count1
Re_call:
BSR Re_cycle
DBNZ Count1,re_call
mov #07T, count1
DBNZ count1,*
Rts

DELAY_500MS: The idea is to repeat the execution of the delay_10ms 50 times, so there is definitely an imprecise place, please forgive me.
mov #50T, Count2
Re
BSR delay_10ms
DBNZ Count2,re
Rts

Main

BSR delay_1ms
BSR delay_10ms

BSR delay_500ms
Again
Nop
JMP again


ORG $fffe
DC.W Main

Freescale mc9s08aw60 Compilation Study notes (vi)