Functions of various registers

Four data registers (eax, EBX, ECx, and EDX)
2 address changes and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
Six segment registers (ES, Cs, SS, DS, FS, and GS)
1 Instruction Pointer register (EIP) 1 flag register (eflags)

1. Data Register
Data registers are mainly used to save information such as the operands and operation results, thus saving the time required to read the operands by occupying the bus and the memory of the FAQ. The 32-bit CPU has four 32-bit General registers eax, EBX, ECx, and EDX. Access to low 16-bit data does not affect high 16-bit data. These 16-bit low registers are named ax, BX, CX, and DX respectively, which are consistent with the registers in the previous CPU.

4 16-bit registers can be split into 8 independent 8-bit registers (ax: Ah-Al, Bx: bh-BL, CX: ch-cl, DX: DH-DL ), each register has its own name and can be accessed independently. Programmers can flexibly process word/byte information by taking advantage of the "severable" feature of data registers.
Registers ax and Al are generally called accumulators. Operations with accumulators may take less time. Accumulators can be used for multiplication, division, input/output, and other operations. They are frequently used. Register BX is called base register ). It can be used as a memory pointer; register CX is called a count register ). During loop and string operations, use it to control the number of loops. during in-place operations, use Cl to specify the number of shifts when multiple bits are moved;
Register dx is called a data register ). When multiplication and division operations are performed, it can be used as the default operand operation and operation, or it can be used to store the I/O port address. In a 16-bit CPU, ax, BX, CX, and DX cannot be used as the base address and address change register to store the address of the storage unit, but in a 32-bit CPU, its 32-bit registers, eax, EBX, ECx, and EDX, can not only transmit data, temporarily store data to save Arithmetic Logic calculation results, but also serve as a pointer register, these 32-bit registers are more universal.
2. Address Change register
The 32-bit CPU has two 32-bit General registers ESI and EDI. Its 16-bit low corresponds to the Si and Di in the previous CPU, and its access to low 16-bit data does not affect the high 16-bit data.
Registers ESI, EDI, Si, and Di are called index register. They are mainly used to store the offsets of storage units in segments. They can be used to address multiple memory operands, it provides convenience for asking storage units in different address formats. The address change register cannot be partitioned into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations. They can be used as general memory pointers. In the running process of string operation commands, they have specific requirements and special features.
3. pointer register
The 32-bit CPU has two 32-bit General registers, EBP and ESP. Its Low 16 bits correspond to the same memory and SP in the previous CPU, and its access to low 16 bits of data does not affect the high 16 bits of data.
Registers EBP, ESP, BP, and SP are known as pointer register. They are mainly used to store the offset of storage units in the stack. They can be used to address multiple storage operations, it provides convenience for asking storage units in different address formats. Pointer registers cannot be partitioned into 8-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.
They are mainly used by the consumer to ask about the storage units in the stack, and stipulate that:
BP calculates the elements in the stack by subtracting a certain offset value from the base pointer register;

SP is the stack pointer register, which always points to the top of the stack.

Note: because the growth direction of the stack is from the high address to the low address, so when the stack is pushed, SP auto-subtraction; when the stack is exited, SP auto-increment;
4. segment register
Segment registers are set based on the memory segment management mode. The physical address of the Memory Unit is composed of the segment register value and an offset.
In this way, two smaller-digit values can be combined into a memory address that can be used to query a larger physical space.
Segment registers inside the CPU:
CS-code segment register (code segment register), whose value is the segment value of the code segment;
DS-data segment register (data segment register), whose value is the segment value of the data segment;
Es -- extra segment register; its value is the segment value of the additional data segment;
Ss -- stack segment register (stack segment register), whose value is the segment value of the stack segment;
FS -- extra segment register; its value is the segment value of the additional data segment;
GS -- extra segment register; its value is the segment value of the additional data segment.

In a 16-bit CPU system, it only has four segment registers. Therefore, the program can directly ask at any time when there are at most four segments in use; in a 32-bit microcomputer system, it has 6 segment registers. Therefore, a program developed in this environment can ask 6 segments at most at the same time. The 32-bit CPU has two different ways of working: real-time mode and protection mode. In each mode, segment registers have different functions. The following is a brief description of the relevant provisions:
Implementation Method:The meanings of the first four segment registers CS, DS, es, and SS are exactly the same as those of the corresponding segment registers in the previous CPU. The logical address of the memory unit is still "segment value: offset format. To explain the data in a memory segment, the offset between the register and the storage unit must be used.
Protection Method:In this method, the situation is much more complicated. The block register is no longer a segment value, but a value called "selector.
5. Instruction Pointer register
The 32-bit CPU extends the instruction pointer to 32-bit and records it as an EIP. The low 16-bit EIP address serves the same purpose as the IP address in the previous CPU.
The EIP and instruction pointer are the offsets of the commands to be run next time in the code segment. In a system with the prefetch command function, the command to be run next time is usually prefetch to the command queue unless the transfer occurs. Therefore, the command queue is not considered when you understand their functions.
In actual mode, because the maximum range of each segment is 64 K, the 16-bit high in the EIP must be 0. At this time, it is equivalent to simply using its low 16-bit IP address to reflect the running order of commands in the program.
6. Mark register
I. Operation Result flag
1. Carry mark CF (carry flag)
The carry mark CF is used to indicate whether the operation generates carry or borrow digits. Assume that the highest bit of the calculation result produces a carry or borrow digit. The value is 1, otherwise the value is 0. This flag is used for addition and subtraction of the number of characters (in bytes), the ratio of the number of unsigned values (in bytes), and the shift between words (in bytes, commands that specifically change the CF value.
2. Parity mark PF (parity flag)
The parity mark PF is used to reflect the parity of the number of "1" in the calculation result. If the number of "1" is an even number, the PF value is 1; otherwise, the value is 0.
PF can be used for parity check or to generate parity bits. In the process of data transmission, in order to provide the reliability of the transmission, assuming that the secondary node uses the parity method, this flag can be used.
3. Auxiliary carry flag AF (Auxiliary carry flag)
In the following cases, the value of the secondary carry flag AF is set to 1; otherwise, the value is 0:
(1) When the word operation occurs, the lower byte is carried to the high byte or the borrow digit;
(2) When the byte operation occurs, the lower 4 bits are carried to the upper 4 bits or the borrow bits.
For the above 6 operation result flags, in general programming, flags CF, ZF, SF, and of are frequently used, the use frequency of flag pF and AF is low.
4. Zero flag (ZF)
The zero sign ZF is used to indicate whether the calculation result is 0. If the calculation result is 0, the value is 1; otherwise, the value is 0. This flag can be used to determine whether the calculation result is 0.
5. Sign SF (sign flag)
Symbol mark (SF) is the symbol bit used to reflect the calculation result. It is the same as the highest bit of the calculation result. In a microcomputer system, the signed number operator uses the complement representation. Therefore, SF also reflects the positive and negative signs of the calculation result. When the calculation result is a positive number, the value of SF is 0; otherwise, the value is 1.
6. Overflow flag)
Overflow sign of indicates whether the result of the addition or subtraction operation of the number of symbols overflows. If the calculation result exceeds the range expressed by the current number of digits, it is called overflow. The value of is set to 1. Otherwise, the value of is cleared to 0 ." Overflow and carry are two different meanings. Do not confuse them. For more information, see the relevant chapter in the computer composition principles course.
Ii. Status Control flag
Status control flags are used to control CPU operations. They need to use special commands to make changes.
1. Tracking mark TF (trap flag)
When the trace flag TF is set to 1, the CPU enters the single-step running mode, that is, each running command generates a single-step interrupt request. This method is mainly used for program debugging. There are no specific commands in the command system to change the TF value of the flag, but programmers can use other methods to change its value.
2. If (Interrupt-enable flag)
The interrupt consent flag if is used to determine whether the CPU responds to the interrupt requests that can be blocked outside the CPU. However, no matter what the value of this sign is, the CPU must respond to the interrupt requests from the outside of the CPU that cannot be blocked and the interrupt requests generated inside the CPU. The detailed provisions are as follows:
(1) When if = 1, the CPU can respond to the interrupt requests that can be blocked outside the CPU;
(2) When if = 0, the CPU does not respond to the interrupt requests that can be blocked outside the CPU.
The CPU command system also has special commands to change the if value of the flag.
3. direction sign DF (Direction Flag)
The direction sign (DF) is used to determine the direction in which the pointer register is adjusted when the string operation command is running. For details, see section 5.2.11-string operation instructions. In the microcomputer instruction system, special commands are also provided to change the value of the Flag DF.
3. 32-Bit Flag register
1. iopl (I/O privilege level)
The I/O privileged flag is expressed by two binary bits, also known as an I/O privileged level field. This field specifies the privileged level required to run the I/O command. If the current privileged level is less than or equal to the iopl value, the I/O command can run. Otherwise, a protection exception occurs.
2. nested task flag NT (nested task)
The nested task flag NT is used to control the iret operation of the interrupt return command. The detailed provisions are as follows:
(1) When NT is set to 0, use the stored values in the stack to restore eflags, Cs, and EIP, and run the regular interrupted return operation;
(2) When Nt = 1, interrupt return is realized through task conversion.
3. Restart the dynamic mark RF (restart flag)
The restart dynamic mark RF is used to control whether debugging failures are accepted. NOTE: If RF is set to 0, it indicates "accept" debugging fault; otherwise, it is rejected. After a command is run successfully, the processor sets the RF to 0. When a non-debugging fault is received, the processor sets it to 1.
4. Virtual 8086 mode mark VM (Virtual 8086 Mode)
If the value of this flag is 1, it indicates that the processor is in the virtual 8086 mode. Otherwise, the processor is in the normal protection mode.