1, in Makefile can only invoke shell script in target, other places can not be output. For example, the following code does not have any output:
Var= "Hello" echo "$ (VAR)" All: ... ..
The above code will not output at any time, not within target, if the above code is changed to the following:
Var= "Hello" all: echo "$ (VAR)" .....
The above code will execute the echo command when make all.
The final printing result is:
echo "" Hello ""
"Hello"
2. Execute the shell command in makefile, one line to create a process to execute. This is also why many makefile have many lines at the end of the "; \ "To ensure that the code is one line instead of multiple lines, so that the makefile can be executed in a process, for example:
SUBDIR=SRC Exampleall: @ in$ (subdir); do echo "building"; Done
As you can see, each line in the For loop is "; \ "End of.
3. All words that begin with $ in makefile will be interpreted as variables in the makefile. If you need to invoke a variable in the shell (or an anchor in a regular expression), you need to add two $ sign ($$). Examples are as follows:
Path= "/data/" all: variable in echo ${path}/*makefile, that is, "/data"/ echo $ $PATH/*shell variables * /
The first ${path} in the example refers to a variable in the makefile, not the PATH environment variable in the shell, which refers to the PATH environment variable in the shell.
The above three points is makefile call Shell should pay attention to the place, write makefile must pay attention to.
[Go] call Shell in makefile