Go deep into the whole process of large-scale Chip Design

Preface

Human's natural sensitivity to visual signals determines the desire for graphic processing hardware performance has become the hottest topic in the current hardware industry. Compared with audio devices that provide audible processing, the current level of graphic processing technology leaves a lot of room for development in graphic processing, which determines that competition in this industry is full of variables, in terms of technology development and marketing strategies, if you are careful, you will not be able to catch up with others. To cope with fierce competition in the industry, designing a higher-performance graphics processing chip has become the most important means for various manufacturers to maintain their own competitiveness. Today, I will make a special trip to understand the whole process of graphic chip design and R & D. In fact, most chip design manufacturers are developing new products based on this program.

Determine the R & D solution and hardware language description

Like any enterprise that relies on production products for development, the first step to design and launch a new GPU is market research and product development plan. During this period, the positioning of products in the future, the main topics of market occupation, and other topics were mentioned on the desktop, the results of the discussion on these issues will ultimately determine the general content of the final product R & D solution: R & D costs, R & D cycles, and resources required during the development process.

Next, we will discuss the specific details of the production process, chip OEM, and other issues from the technical aspects of the R & D solution. Physical parameters, such as the number of integrated transistors, are determined within the scope of the cost; then there are many factors that determine the choice in the chip foundry that conforms to the production process, of course, the first point is to provide the technical level required for the production of chips, such as 0.15 micron, 0.13 micron, or even 90 Nano, followed by the product quality and price factors of the foundry. Of course, most of the time when the chip is designed, it is planned to use a relatively advanced process to ensure that the selected Foundry (that is, the chip production company such as TSMC)
) It is very important to complete the related process transformation when the chip design is completed and the projection starts. If you make a wrong judgment on this point, it will cause huge losses to the company, because the graphics chip industry is the most fast-performing industry, if the production process has been decided, if you want to revise the process indicators, the work will continue for several months, the workload is no less than that of a new chip!

After all the preliminary steps are determined, we will start to show the design of the chip architecture in the main part of this article. A design team is organized to define the technical features supported by the GPU and develop a calendar of the overall design work (for example, Team 1 completes the design of the anti-sawtooth unit within three weeks ).

Before in-depth introduction to the chip design process, let's take a look at the general design process of chip manufacturing companies. Currently, the design of the chip architecture is generally completed through the hardware design language Hardware Description programming ages (HDL). The so-called hardware design language (HDL), as the name suggests, it is a language used to describe the hardware working process. Currently, many of the commonly used products are called VHDL and Tilde. Code written in these languages can be used to generate the cabling table and layout diagram of logical door circuits with dedicated synthesizer, which will be the main production basis for future delivery to the chip foundry. For hardware design languages (
Generally, this is basically not accessible to people. Here, we will only give you a brief introduction: in the form of program code, there is not much difference between HDL and C, however, their actual functions are completely different. For example, the following is a very basic statement in the language of OpenGL:

Always @ (posedge clock) q <= D;

This is equivalent to a condition judgment statement in C, which means that when the clock has a rising edge signal, the output signal 'D' is stored in 'q '. Such statements describe the basic data exchange mode between the cache and video memory composed of the trigger circuit. The integrated software generates a circuit based on the working mode of the door circuit described by the Code. In the design phase of a chip, engineers compile the HDL code by using the OpenGL language to design all the work units in the chip, and also decide all the technical features that the chip can support. This phase usually lasts for three to four months (depending on the size of the chip project), and is the basis of the entire design process.

After the above work is completed, it will enter the product design verification phase, usually one or two months. The task at this stage is to ensure that there is no defect in the design scheme for the final delivery of the chip to the foundry, that is, the product bug we usually call ". This phase is an important step for any chip design company, because if the chip design cannot work as properly as it was designed after it is produced, that not only means that we will continue to invest more money to modify the design, but will also lose the lead in the speed at which the graphics chip industry attaches the greatest importance to the product launch. The entire verification process is divided into several processes. The basic function test verifies that all the door circuits in the chip can work normally. The workload simulation test is used to verify the performance of the door circuit combination. Of course, there is no real chip in the physical sense at this time, and all these tests still pass
Programmed to simulate.

Next, the verification work starts to run the branch in parallel. A team is responsible for static timing analysis of the chip circuit to ensure that the finished chip can reach the designed clock speed; another team mainly consists of analog circuit engineers to analyze and modify the storage circuit and power supply circuit. Compared with the correction work of digital circuits, simulation engineers work much harder. They need to carry out a lot of complex numbers, differential equation calculation and signal analysis, even using computers and specialized software is a headache. At this time, many tests and verification work are carried out in the simulated state. Finally, after all the above work is completed, A connection table and circuit diagram generated by the integrated software used for generating input and output door circuits are complete.

However, graphic Chip designers will not immediately deliver this solution to the manufacturers because it will accept the last test, which is what we usually call field programmable gate array) the field programmable gate array is used to verify the final functions of the design. For nv30, which integrates more than 0.1 billion transistor super-complex chips, during the entire design and simulation test using hardware design language (HDL, it is necessary to repeatedly describe billions of commands on the entire chip and store "massive" data. Therefore, the hardware that executes related tasks is almost abnormal. We can see from the NVIDIA lab below.

 

11 Sunfire 6800 servers provided by Sun Microsystems are 6 feet tall. Each server is equipped with GB of memory and the unit price is about one million USD.

 

A rack-type server consisting of a 1u unit of racksaver. Each 1u unit can be configured with two mainboards and two to four Pentium 4 Processors. The entire system includes 2800 CPUs for parallel operation.

This is NVIDIA's hard disk array cabinet. Each cabinet is full of hard disks, providing storage capacity for those servers above "not bottom.

(Editor: The above devices are used for the design of 0.1 billion-level ultra-large-scale integrated circuits. For general ICPs, a general PC workstation or Unix workstation can meet the requirements)

FPGA simulation of programmable gate array

FPGA can be used to complete the functions of any digital device, from high-performance CPUs to simple 74 circuits. FPGA is actually a logical component that contains a large number of door circuits, but the definition of each of its doors can be defined by users, such as the same blank sheet of paper or a pile of wood. Engineers can use the traditional schematic input method, or a digital system can be freely designed in a hardware description language. Through software simulation, we can verify the correctness of the design in advance. After the PCB is complete, you can use the online modification capability of FPGA to modify the design at any time without changing the hardware circuit. Therefore, the use of FPGA to develop digital circuits can greatly shorten the design time, and more importantly, it can greatly reduce the cost of investment and time consumption of finished chips after repeated modifications, A dollar FPGA (the current maximum capacity FPGA) costs a little compared to a finished chip that costs millions of dollars.

(Editor: Well, the above text references the text in the beginner's portal on this site. It seems that this article has been widely used)

In this regard, ATI and NVIDIA both use an FPGA verification system named ikos. Ikos consists of multiple plug-in cards, each of which is an FPGA array consisting of many large-scale FPGA blocks. Since the r300 and nv30 generations, the graphics chip has become the most complex ASIC chip, and one or two FPGAs cannot be used to complete the verification. Such a professional FPGA verification device must be used. of course, FPGA is not perfect, and its inherent disadvantage is that the operating speed is not as fast as the ASIC chip.
Compared with GPUs with a 200-300 MHz running frequency, ikos is only running at dozens of megabytes of Hz. of course, these shortcomings are no big deal in the product design process. it is responsible for the final verification of the implementation of the chip design function. You can enable ikos to run normally as the display part of the system and develop and verify the driver, of course, it is not impossible for you to run a game on such a system, but it is good to maintain several frames per second.

NVIDIA verification lab

This is the case where ikos is used in the NVIDIA ikos lab to simulate nv30. Isn't it incredible that it is difficult to associate such a large red box with a video card chip. The tester is running Windows2000 in this nv30.

 

Casting and production samples and correction

After a series of verification work, this process can come to an end, and several revised design schemes have been sent to the chip foundry to start the production of chips. it usually takes four weeks for the foundry to get the design scheme and deprecate the first batch of products. However, during this period, the designers are still at ease, continue the simulation test of the chip and the design of the printed PCB (printed circuit boards Printed Circuit Board), which has produced the official public board ". four weeks later, the first batch of products went offline. This is what we call the "A0" version. (Editor: "engineering samples ")

Generally, the A0 version will produce less data, and their main purposes are to be tested and modified. Some of them are sent to the development team for further testing and troubleshooting, the other part is delivered to the relevant card board manufacturer for relevant testing and design. Because we now have a real chip, the error detection method is certainly different from the previous simulation method. The FIB (focused ion beam) system is introduced here to check the error process. To put it simply, the FIB system is equivalent to a variety of surgical instruments that we usually see in hospitals that rely on beam energy for surgery. They can not destroy the chip function, modify the door circuit level of the chip-cut off the original or set up a new door connection, no matter which layer of the circuit you need to modify is the metal wiring of the chip, it will not cause any physical damage to the chip.

This is a fib device used by NVIDIA.

 

Of course, in addition to fib equipment, there are also many other testing methods, such as this machine is also a device that detects chip defects, the working principle is completely different, in fact, it is a high-performance atomic electron microscope. The following figure shows the appearance of an NVIDIA chip at a magnification of 45,000 X. What we use in the red line frame is the defect of the chip. Generally, this defect is caused by the mixing of atoms of some other material into high-purity silicon crystals. This machine can identify the type of the atom mixed in and determine the possible cause of the atom going into this part of the chip, so as to take measures to avoid this situation and improve the yield rate.

After all the defects have been corrected, the final design will be delivered to the foundry for production, and the production will not be as small as the A0 version, however, it is not the final production version. When the basic skills verified above are correct, the chips produced this time should undergo various tests related to officially listed products: product compatibility, operating temperature, peripheral power supply circuit stability, signal integrity, etc. until the product can be listed as a product, then the chip producers can put into mass production.

In the final testing process, a large number of GPUs were to be tested. During the convenience period, GPU sockets were made on the graphics card, independent GPU chips can be tested as long as they are plugged in. Of course, these sockets are designed for specific GPU chips and can only be used to test the pin to define the same GPU. Some may say that it would be nice if the video card on the market is also made of this plug-in design and can be continuously upgraded. Let's not talk about the definition of each chip pin. If this is not a problem, we must at least ensure that the video memory can provide data to the new core for Synchronous Bandwidth growth. Therefore, the GPU socket design on the video card is destined to only exist in the lab.

In fact, the socket principle in the chip design process is also applicable to other products. It is also common in the testing process of the Motherboard chipset. Look at the above nforce 2 motherboard, its North Bridge Chip is also placed on the socket, of course, this is a digress.

 

At this stage, many chips will be used for various tests, that is, waiting to test a bunch of quadro4 chips.

Conclusion

Calling, the process of developing a new video card is really better than that of the "Long Journey", and all the small series are tired, let alone the hard work and wisdom of the engineers involved in R & D. Through systematic product R & D and interlocking program formulation, we can also see the strong energy of Western industry in scientific theory systemization and industrialization. This is also worth learning.