Go SDRAM Drive Notes

1.SDRAM burst Mode:sdram is a command-type action device, even if read and write data only one must first under the command can be used, in order to increase work efficiency, produced a kind of transmission command, write multiple data mode, this is burst mode. Burst mode is a high-speed read-write pattern that works with an internal column address generator, as long as the initial column address is set, and the subsequent address can be generated automatically by the Internal column address generator.

2. Why do precharge action? Closing the functioning SDRAM bank is an end command, which can be followed by a new command. I think this is related to the internal management of SDRAM. (This is from the Internet, the feeling is not enough detailed, also do not understand).

3. Auto Refresh function? There is a refresh problem with dynamic memory (RAM). Here the main use of automatic refresh, every time to the SDRAM to send a refresh command.

4.SDRAM Address line: In our general use of what SRAM Ah, psram Ah, ram Ah, generally, there are how many root address lines, and then can calculate the addressing space, such as there are 11 address lines, the addressing space is 2 of 11 square minus 1. But SDRAM is a broken address and line address, row, column address line is multiplexed, so sometimes we see that the address space is mostly large, but look at the location of the line how many root ah, hehe. SDRAM generally has 2 bank lines, divided into 4 banks, in some of the processor's SDRAM control module, these two lines may be mapped to the address line of some two root. The general chip often writes the chip configuration according to the following way, for example 4Meg x 4 x 16, that this chip is 256Mbits. 16 of the data line is 16, the middle of a 4 is only 4 banks, each bank is 4Meg.

Initialization of 5.SDRAM: SDRAM must be initialized before it can be used after power on. This process of operation is standard. The process is as follows:

A:precharge

B:auto-refresh

C:load Mode Register

D:normal Read/write

After power on the input initialization command value, at least 100us delay (this is actually very easy to meet, hehe).

After entering the Precharge command, because all banks must be precharge, so A10 this pin to be set to high, so after precharge to do a read operation, The main thing about this operation is that the address set in the SDRAM addressing space must be A10 high.

After entering the Auto-refresh command, usually with a few words empty operation or read what kind of, anyway to achieve the purpose of delay, so that SDRAM has time to complete the refresh.

After that is to set the SDRAM mode register, this register generally set the burst length, Cas,burst type, operation mode, also is to set the SDRAM is working in a single read or write operation or burst operation. The setting of this register is also set by the address line, so you have to do an operation after issuing the Load Mode Register command, but the value of the outgoing address line on the SDRAM is the value you want to set. Here it is necessary to remind that this operation is a 8-bit operation, remember to remember.

After the mode register is set, it enters normal operation mode.

In fact, the specific operation should be combined with the SDRAM control module of the selected processor to set. A more intuitive understanding of these initialization commands is to analyze them with logic analyzers.

It is important to remind you of the CAS parameter here. Also SDRAM must be refreshed, so the refresh rate can be calculated according to the manual, but the high point of setting is also possible. Often SDRAM have a working frequency, but also can work at a lower frequency, such as PC133, you work to 100 is also possible, setup basically does not need to modify.

6. Basic read and write operation: the basic reading operation of SDRAM requires the control line and address line to issue a series of commands to complete. The Bank Activation Command (Active) is issued first, and the corresponding bank address (BA0, BA1) and the line address (A0~A12) are latched. After the bank activates the command, it must wait longer than the TRCD (SDRAM's RAS to CAS delay metric) time to issue the Read command Word. CL (CAs delay value) after a working clock, the readout data appears sequentially on the bus. At the end of the read operation, a pre-charge (precharge) command is issued to the SDRAM to close the activated page. Wait for the TRP time (precharge) command to close the page that has been activated. Wait for TRP time (after the Prechareg command, after the TRP time, before you can access the row again), you can start the next read, write operations. SDRAM read operation only burst mode (Burst modes), burst length of 1, 2, 4, 8 is optional.

The basic write operation of SDRAM also requires the control line and address line to issue a series of commands to complete. The Bank Activation Command (Active) is issued first, and the corresponding bank address (BA0, BA1) and the line address (A0~A12) are latched. After the bank activates the command, it must wait longer than TRCD to issue a write command word. Write commands can be written immediately, and data should be written to the DQ (data line) in turn. Delay TWR time after the last data is written. Issue a pre-charge command to close the activated page. After you wait for TRP time, you can expand the next operation. Write operations can have both burst and non-burst write two kinds. Burst length same as read operation.

7. Other: We sometimes see some schematic diagram on the data line is reversed, in fact, this does not matter, reverse over, write in is the opposite, but read out and reverse, anti-anti two times just right.

Extended to the DDR, in fact, the DDR is the SDRAM outside added a turtle shell. So the initialization is the same. Of course, DDR one is more than a clock frequency reversed clock, so there are 2 phase difference 180 degrees of the clock. These two are usually generated with the same clock source, and the consistency will be better. There are 2 more DQS, this is a timing requirement, the General CPU control module has been set up. If you use a CPU that does not contain a control module, then use the FPGA to make a control module, then you need to study the timing carefully.

In some processor control modules, due to EMI settings, the Address line mapping relationship is complex, so the calculation will be more cumbersome, generally if there is no mapping, it is easy to operate.

Go SDRAM Drive Notes