How do wiring engineers fully control clock signals?

In digital circuit design, the clock signal is a signal that oscillates between the high and low states, which determines the circuit performance. In applications, the logic may be triggered at the rising or falling edge, or at the same time at the rising or falling edge.

As there are many cases of overflow of a given clock domain, it is necessary to insert a buffer tree to sufficiently drive the logic. The Clock Tree usually carries the latency, distortion rate, minimum power, and signal integrity requirements that must be met by cabling engineers.

When the circuit is transferred from the former process designer to the later process wiring engineer, the clock overview and chart are considered to be the most critical information that must be communicated. For many years, due to miscommunication, the design work of several hours, days, or even weeks has been in vain and requires a full set of re-synthesis, including the Clock Tree. Before wiring, an excellent clock is used to synthesize a timely ordered constraint. The constrained clock definition may appear on the top pad or pin of the module;

It may appear in macro output, such as lock delay loop (DLL) or Phase-lock loop (PLL); or the generated clock may appear on the Division register. These clock definitions may or may not be the areas where cabling engineers need to define clock roots to achieve optimal latency and balance distortion rates between different working modes.

The CTS process of the physical design process will be greatly optimized by communicating high-level information about the information and understanding how the cabling engineer uses the information.

Effective CTS design skills

Some of the following techniques have been used in the industry for many years. However, based on the experience of the past few years, they are still worth repeated use.

Use medium-to-high-intensity drives for clock roots. This enables the Clock Tree to have a proper start point. However, do not use the maximum driving strength in the database. If there is no problem with signal integrity (SI) analysis or on-chip change (VOC) analysis, it can be used in subsequent designs.

If the clock division registers and their synchronization registers need to work in a separate test mode, make sure that they are driven by the reusable logic. This increases latency at the input end in test mode without affecting all other registers of the clock driver generated in this function mode. (Divide-by) registers are not balanced with any downstream registers. The smaller the number of registers in the green color gamut, the faster the clock speed is than that in the purple color gamut.

Figure 1 register clock division register

Figure 2 shows the possibility that each downstream register and division register can have a very small clock by reusing an input and a balanced clock by reusing another input.

Figure 2 Downstream register and division register

If necessary, insert a dedicated reset drive. In some cases, several registers will be used for Synchronous Reset. Those registers may not need to be balanced by the same register.

As shown in figure 3, since no centralized policy is adopted, the software will try to balance the blue register after the gate logic, and each pink register is included in the reset synchronization logic.

Figure 3 register after the balanced gate Logic

If they are separated from other registers in their respective dedicated drives, this can be easily handled during cabling. Figure 4 shows how to insert and easily identify a placeholder (place-holder) or exclude a buffer during hand-off communication, let the wiring engineer know where the balance problem may occur.

Figure 4 insert and easily identify placeholders or exclude Buffers

Provides more than expected clock charts and a large number of clock introductions. When the current process design is ready to provide network tables for cabling, they are very familiar with the design and clock requirements.

In some cases, the initial CTS design will prompt the situations where the ideal values used in the prewiring timing constraints cannot be implemented in the actual physical design. If you provide a precise clock graph and a network table with information about the clock principle, you can identify the problem faster.

A general diagram is useful, or a diagram that represents all the Clock types in the design (including the clock control logic. This is either a drawing software, or a diagram generated using software such as a circuit diagram capturing tool, or even hand-drawn and stored as a PDF document or a diagram sent to a wiring engineer by fax. This figure is worth a thousand words in the process of trying to directly get the clock format for multiple calls or email communication. As charts may be complex and complex, you need to provide corresponding introduction documents, this includes an explanation of the generated clock, details of any clock-controlled or reusable pattern, and distortion rate balancing and latency requirements.

This is required for each working mode because each mode must be used during the insertion of the clock tree. Registers may eventually provide a balance for the functional mode, but if we do not carefully, the test mode can be extremely unbalanced.

These details are required if the clock uses DLL or other macros or it passes the gate logic. If necessary, it is possible to combine and balance those types of macros. For the gate logic, if one pin is connected in one mode, but other pins in the same unit are connected in another mode, the cabling tool identifies this situation as a "re-aggregation Clock ". Although wiring tools can solve these problems, a better solution may be to force the tool to view this pin during time insertion, rather than other pins.

CTS in industry software tools

Industry software follows the specifications and guidelines of designers and uses powerful tools to promote Clock Tree Synthesis. Information related to the clock root insertion point, delay, distortion rate, and transition target derived from the previous process, as well as detailed information for the door control logic, through registers and cross-domain relationships, can be directly transplanted to the CTS Tool. Then the wiring engineer will determine the buffer type to use, optimize iteration and spacing, and wiring requirements such as the screen and metal layers.

Before inserting a clock tree, you can use a line to ensure that an endpoint exists for balancing. You can also prompt and evaluate the door control logic, branch of clock root exclusion, IO endpoint, and re-aggregation instance.

The clock tree may only contain buffer units or series inverters. Most of today's technologies have special clock buffering and clock reverse-phase units that provide a balanced rise and fall time to help ensure that the duty cycle is not compromised. You can also integrate other requirements, such as the level in the clock tree or the maximum fan-out of each clock unit.

Conclusion

In addition to all the factors discussed above, cabling engineers are likely to try clock-controlled la S, clock cabling guidelines, and plane layout adjustments. CTS replacement usually runs when the distortion rate, delay, and transition target are rarely adjusted. The trial and error methods help provide excellent coordination.

If the previous process understands how CTS works and communicates the clock structure at the very beginning, the wiring engineer will be able to take over the task more easily. The time originally scheduled for CTS in the schedule can be used to fine tune and improve "your clock", rather than simply trying to insert it into "My wiring ".