How to process signals in Multi-Time Domain Design

In the design of multiple clock domainsSignal Cross-Time DomainHere we can usePing-pong operations. The Ping-Pong operation process is as follows:The input data stream is allocated to two data buffers when the data stream is divided into two data buffers through the 'input data selection unit '.The data buffer module can be any storage module. Common storage units include dual-port RAM (DPRAM), single-port RAM (spram), and FIFO.

In 1st buffer cycles, the input data stream is cached to "data buffer module 1 ";

During the 2nd buffer period, the input data stream is cached to "data buffer module 2" by switching the "input data selection unit ", at the same time, the 1st cycle data cached by "data buffer module 1" is sent to the "data stream operation processing module" for calculation through the "input data selection unit" selection;

In the first buffer cycle, the data stream is cached to "data buffer module 1" by switching the "input data selection unit ", at the same time, the data in the 2nd period cached by "data buffer module 2" is switched over to the "data stream operation and processing module" for calculation. This loop.

The biggest feature of Ping-Pong operations is to switch between "input data selection unit" and "output data selection unit" by cycle and mutual cooperation, the buffered data stream is sent to the "data stream operation and processing module" for calculation and processing without stopping. Taking the ping-pong operation module as a whole, we can view data at both ends of this module. The input and output data streams are continuous without any pause. Therefore, it is very suitable for pipeline processing of data streams. Therefore, Ping-Pong operations are often used in pipelines.AlgorithmTo complete seamless data buffering and processing. It can also save buffer space.

Another method is to use FIFO for data transmission between different clock domains, such as AD data collection at one end of FIFO and PCI bus of the computer at the other end, assume that the ad acquisition rate is 16-bit 100 k SPS, the data volume per second is 1.6 K × 16 bit = Mbps, while the PCI bus speed is 33 MHz, and the bus width is 32 bit, the maximum transmission speed is Mbps, and data is buffered using FIFO between two different clock domains. In addition, FIFO can be used for data interfaces of different widths, such as single-chip microcomputer bit 8-bit data output, while DSP may be a 16-bit data input, when the single-chip microcomputer is connected to the DSP, the FIFO can be used for data matching.

 

Signal communication between different clock domains is requiredSynchronous processingThis prevents the sub-logic from being affected by the sub-State signal of the first-level trigger in the new clock domain.Two-level synchronizers can be used for a single control signal, such as level, edge detection, and pulse. FIFO, dual-port RAM, and handshaking signals can be used for multiple signals.

 

There are many cases. If you have a simple answer, the answer is:Cross-time-domain signals must be synced with the synx to prevent sub-steady state transmission.. For example, if a signal in the clock domain 1 needs to be sent to the clock domain 2, after the signal is synchronized to the synchronization of the clock domain 2 before the signal is sent to the clock domain 2, to enter the clock domain 2. This synchronizator is a two-level D Trigger whose clock is a clock in the clock domain 2. In this case, we are afraid that the signal in the clock domain 1 may not meet the set-up holding time of the trigger in the clock domain 2, but produce the sub-steady state because there is no inevitable relationship between them and it is asynchronous. This can only prevent the spread of the Asian steady state, but cannot ensure the correctness of the collected data. Therefore, only a few digits of signals are usually synchronized. For example, the control signal or address. When the address is synchronized, the gray code is generally used for this address, because the Gray code changes only one bit at a time, which is equivalent to only one synchronization machine at a time, which can reduce the error probability, this method is used to compare the read/write address size in the asynchronous FIFO design.
If a large amount of data is transferred between two clock domains, asynchronous FIFO can be used to solve the problem.