(ii) Memory addressing

This article describes the fragmentation and paging mechanism of Linux on the X86 platform.

The MMU (Memory control unit) converts the logical address into a linear address through the hardware circuit of the segmented unit, and then translates the linear address into a physical address by the hardware circuit of the paging unit:

Logical address: Contains the address used in a Machine instruction language directive to specify an operand or an instruction. Each process has its own code snippet, data segment, and the logical address is the offset address relative to the code snippet or data segment.

Linear Address: The program code generates a logical address, and the logical address is converted to a linear address by the hardware circuit of the segmented unit. The range of linear addresses is generally related to the number of CPUs, and if 32 is the CPU, it can express a linear address of up to 4G.

Physical Address: Memory unit addressing for the physical memory chip. Its range is related to the number of bits of address bus.

Hardware segmentation for X86:

A logical address consists of two parts: the segment identifier and the offset of the relative address within the specified segment.

The processor provides 6 segment registers, Cs,ss,ds,es,fs,gs;

Segment Descriptor: 8 bytes, used to store the start address of the segment, the segment size, storage permissions, and so on. stored in the GDT or LDT.

Segment Selector (segment identifier): 16 bits, used to find the segment descriptor, stored in the segment register.

Segmented process: The segment identifier specified by the logical address is loaded in the segment register, the segment identifier specifies the beginning address of the segment descriptor, the segment start address of the corresponding segment is found in the segment description, the beginning address of the segment is shifted left N (n= address bus number of bits-cpu), and the offset within the segment specified by the logical address is added to get the

Segments of Linux:

Linux uses fragmentation in a very limited way, using fragmentation only under X86 institutions (some architectures have limited support for fragmentation, especially RISC).

Linux processes running in the user state use a pair of identical fields to address the instruction and data: The user code segment and the user data segment; All Linux processes running in the kernel state use a pair of identical segments for instruction and data addressing: The kernel snippet and the kernel data segment. Their segment start address is 0x0, then the logical address and the linear address are consistent under Linux, i.e. the value of the offset field of the logical address and the corresponding linear address are always the same.

X86 Hardware Paging:

The paging unit translates the linear address into a physical address.

For efficiency reasons, linear addresses are divided into groups of fixed-length units, called pages. The linear address inside the page is mapped to a contiguous physical address. The paging unit divides all the ram into a fixed-length page box.

A data structure that maps a linear address to a physical address is called a page table. The page table is stored in main memory, and the page table must be initialized appropriately before the paging unit is enabled.

General Paging:

Starting with 386, the Intel processor's paging unit processes 4KB pages. The 32-bit linear address is divided into 3 domains: directory (directory) up to 10 bits: Table (page table) Middle 10 bit: offset (offset) Lowest 12 bit, linear address conversion is done in two steps, each step is based on a conversion table, the first conversion table is called the page catalog table, The second table is called the page table, and the two-level pattern is used to reduce the amount of RAM required for each Process page table. Each active process has a page directory assigned to it, the page table is allocated when it is actually needed, the physical address of its page directory is stored in the CR3 of the control register, the CR3 and the Dirctory field of the linear address determine the directory entry in the page directory, and then the table entry of the page table is determined by the linear address of the tables field. Then match the offset field to find the physical address within the page box.

Extended Paging:

Starting with Pentiun, X86 introduces extended paging with a page box size of 4MB, and extended paging translates large segments of contiguous linear addresses into the physical address of the response. The kernel can not convert the intermediate page table. Directiory (10-bit): OFFSET (22-bit);

Physical Address Extension paging mechanism:

The RAM capacity supported by the processor is limited by the number of address pins connected to the address bus. When a large server needs more than 4GB of RAM, Intel increases the pin from 32 to 36 bits on its processor, and introduces a paging mechanism for physical address extensions to convert 32-bit linear addresses to 36-bit physical addresses.

Paging for 64-bit systems:

The 32-bit system uses a 2-level paging mechanism, and the 64-bit system uses an additional paging mechanism for efficiency and RAM capacity considerations. The number of levels used depends on the type of processor.

Paging for Linux:

Linux uses a common paging model for both 32-bit and 64-bit bears, currently using a four-level paging model: page Global Catalog: Page Parent Directory: Page Intermediate directory: Page table.

The page global catalog contains the addresses of several pages of the parent directory, and the page ancestor directory contains the addresses of several pages of intermediate-level catalogs, which in turn contain the addresses of several page tables. Each page table entry also points to the Night Song page box. The linear address is therefore divided into 5 parts.

There is no 32-bit system to start the physical Address extension, Linux uses a 2-level model: page Global catalog and Page table, page ancestor directory and page intermediate directory full 0;

32-bit systems that have physical Address extensions enabled use the Level 3 page table.

Whether a 64-bit system uses three-level or four-level paging depends on the hardware's partitioning of the linear address.

(ii) Memory addressing