In-depth analysis of major and minor issues in the startup code of S3C2440 I. About the size-end settings in ads1.2 and the impact on the compiled code. The following describes how to compile the code in the online code segment mode, the content of the generated binary file is compiled in the big-end mode. The content of the generated binary file can be seen from the above: Their byte order is the opposite, that is, the size setting in ads1.2 affects the byte order of the final binary file. Ii. Code related to the size tube in the startup code of S3C2440 option. inc
GBLLENDIAN_CHANGE ENDIAN_CHANGESETL{FALSE} GBLAENTRY_BUS_WIDTH ENTRY_BUS_WIDTHSETA16
Related code in 2440init. s
AREA Init,CODE,READONLYENTRYEXPORT__ENTRY__ENTRYResetEntry;1)The code, which converts to Big-endian, should be in little endian code.;2)The following little endian code will be compiled in Big-Endian mode.; The code byte order should be changed as the memory bus width.;3)The pseudo instruction,DCD can not be used here because the linker generates error.ASSERT:DEF:ENDIAN_CHANGE[ ENDIAN_CHANGEASSERT :DEF:ENTRY_BUS_WIDTH[ ENTRY_BUS_WIDTH=32bChangeBigEndian ;DCD 0xea000007][ ENTRY_BUS_WIDTH=16andeqr14,r7,r0,lsl #20 ;DCD 0x0007ea00][ ENTRY_BUS_WIDTH=8streqr0,[r0,-r10,ror #1] ;DCD 0x070000ea]|bResetHandler]bHandlerUndef;handler for Undefined modebHandlerSWI;handler for SWI interruptbHandlerPabort;handler for PAbortbHandlerDabort;handler for DAbortb.;reservedbHandlerIRQ;handler for IRQ interruptbHandlerFIQ;handler for FIQ interrupt;@0x20bEnterPWDN; Must be @0x20.ChangeBigEndian;@0x24[ ENTRY_BUS_WIDTH=32DCD0xee110f10;0xee110f10 => mrc p15,0,r0,c1,c0,0DCD0xe3800080;0xe3800080 => orr r0,r0,#0x80; //Big-endianDCD0xee010f10;0xee010f10 => mcr p15,0,r0,c1,c0,0][ ENTRY_BUS_WIDTH=16DCD 0x0f10ee11DCD 0x0080e380DCD 0x0f10ee01][ ENTRY_BUS_WIDTH=8DCD 0x100f11eeDCD 0x800080e3DCD 0x100f01ee]DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.DCD 0xffffffffDCD 0xffffffffDCD 0xffffffffDCD 0xffffffffb ResetHandler
We can see that in option. Inc, endian_change is set to false, and the program runs bresethandler directly. By default, S3C2440 is in the small-end mode, and the setting in ads1.2 is also in the small-end mode.
Now, let's set the interrupt mode in ads1.2 and set endian_change to false to true. Now the problem is coming. See the analysis below. During program compilation, one of the following three commands will be placed at 0 address bchangebigendian according to the entry_bus_width macro; DCD 0xea000007
Andeqr14, R7, R0, LSL #20; DCD 0x0007ea00
Streqr0, [r0,-R10, Ror #1]; DCD 0x0720.ea actually provides the same functions for these three commands, but only adjusts the byte order according to the data bandwidth, changebigendian redirects to 0x24 for execution. changebigendian is used to change the size-end mode of S3C2440 through coprocessor C1 in CP15. Let's take a look at these three commands. Because we have already set the large-end mode in ads, these commands are compiled in the big-end mode, while the S3C2440 is still in the small-end mode. How can we execute commands in the big-end mode in the S3C2440, for example, bchangebigendian; DCD 0xea000007 ??? The reason is as follows: if a memory system is configured as one of the memory formats (such as small ends) based on an ARM chip, and the actually connected storage system is configured in the opposite format (such as large ends ), therefore, only instructions in the unit of words, data loading, and data storage can be reliably implemented. Unexpected results may occur for access to other storage devices. That is to say, in the 32-Bit mode, the size-end mode has no impact on command pointing, data loading, and data storage. (Note: If the actual memory format does not match the Memory Format of the chip, only data access in words is correct. Otherwise, unexpected results may occur .) The machine code of bchangebigendian is 0xea000007 in the big-end mode. In the 32-Bit mode, the four bytes are respectively: 07 00 ea. If the bchangebigendian command is executed in the 8-Bit mode, it must be manually changed to 0x0720.ea to be executed by the S3C2440 command in the small-end mode. The order of storage in the memory: the order from the low address to the high address is 07 00 EA, and when the S3C2440 command is obtained in the small-end mode, it is 0xea000007. The bchangebigendian command is manually changed to 0x0007ea00 to be executed by S3C2440 in the small-end mode in 16-Bit mode. The order of storage in the memory: from the low address to the high address is 0007 ea00, respectively, when the S3C2440 command is obtained in the small-end mode, it is obtained as 0xea000007. It is similar when the code of the C1 register in CP15 is modified later. Welcome to the discussion. Please point out any errors. Thank you!
