Initial knowledge of the cache

1. What is the cache?

The name cache is used to address concepts that exist in two physical worlds, the hardware cache and the cache mechanism. Here are the separate sections.

Hardware cache: The hardware cache is an object that can be seen with the naked eye and can be touched by the skin, which is made up of SRAM (Static random-access memory) (in the computer hardware system, the main memory by the DRAM (dynamic Random-access memory) composition. Hardware cache in the CPU, directly with the register for data transmission.

Cache mechanism: There are two storage areas, zone A, area B, region B is greater than region A, region a holds the most commonly used data in area B. Because region A is smaller than region B, it takes less time to find a single data in region A. Region A always maintains the most commonly used data in region B while the program is running. Such a mechanism is called the cache mechanism. With the cache mechanism, we can access the data needed by the program more quickly. Of course, it is worth noting here that the cache mechanism is effective because of a feature of the program, locality. This feature of the program can simply assume that each program accesses only a few data and often accesses them (if you want to learn more about locality, you can refer to the reference material given at the end of this article). The cache mechanism is as follows.

In practice, we need to determine from the context whether the cache here refers to the hardware cache or the cache mechanism. The hardware cache is essentially a storage area with very high hardware access speeds and uses the cache mechanism on this storage area. Therefore, the core of the relevant knowledge introduced in this paper is the cache mechanism. The hardware cache simply adds a better hardware material.

2, the hardware cache and the cache mechanism in the computer system distribution

The memory hierarchy in the computer system, as shown,

For the hardware cache. L1cache,l2cache,l3cache is a hardware cache that exists in the CPU.

For the cache mechanism. There is a cache mechanism between L1 and L2, that is, the L1 is the L2 cache (if the CPU wants to access the data on the L2, then the CPU accesses the upper L1. If you have the data you want, L1 directly back to the CPU, and if not, search for the desired data from the L2, save it to L1, and finally return the data to the CPU). Similarly, L2 is L3 's cache,l3 is L4 's cache, and so on.

3, the cache read and write (here refers to the cache mechanism)

In the cache mechanism, the operation mechanism of the read operation is the same. Assuming that the CPU wants to access data B on level k+1, its address is a.

The 1th step, according to address A to determine the data B at the level K, if in, return to CPU data B, we call the cache hit occurs; if not, we take step 2nd, and say cache miss occurs;

2nd, on level k+1, search for data B according to the address, the block where data B is located replaces the corresponding block on level k with the replacement rule and returns the data B required by the CPU. Note: This is where the block where data B resides is copied to the upper layer, not just data B. A block contains not only data B, but several adjacent data items. The transfer of data between layers and layers is carried out in blocks to improve transmission efficiency. The size of the block between layers and layers is not the same, generally, the closer to the bottom, the larger the block, the block between the 32-64 bytes.

A more detailed description of the details, more cumbersome, not to repeat here, just read the first chapter of the following resources, and remember that the copy is block and not just a single data item, that is understandable.

The cache's writing is based on the cache reading, reading comprehension, writing nature to understand.

4, the cache classification

Depending on whether the cache is stored with instructions or data, it can be divided into I-cache and D-cache.

According to the number of each set, the number of cache line can be divided into directed-mapped caches (multiple sets, each set in the cache line only one), set associative caches (multiple set, There are more than 1 cache line in each set, fully associative caches (only one set), respectively, such as left, middle, and right.

5. References

<<computer Systems A programmer ' s perspective>> Second edition p559-p615

Initial knowledge of the cache