Intel microprocessor Learning Note (iv) memory paging

The paging mechanism (memory paging mechanism) is starting from 386. Linear addresses are transparently converted to physical addresses through a paging mechanism.

The linear address is the address generated by the program;

Physical addresses (physical address) are the actual memory addresses accessed by the program.

The registers associated with the paging mechanism are CR0, CR1, CR2, CR3, and CR4, and are all 32-bit registers.

　　

Figure One control register

　　

1. The PG bit of CR0 is 1 o'clock, paging starts. Otherwise, the linear address is the physical address. The paging mechanism works in both real mode and protected mode.

2. CR3 includes the page directory base address as well as the PCD and PWT bits. If PCD is 1, the PCD pin becomes logic 1 on the non-paged bus cycle, which allows the external hardware to control level two advanced buffer memory. The PWT bit also acts on the PWT pin on the nonpaged bus cycle, and is used to control the write-through (Write-through) cache memory in the system. The page directory base address is used to address page catalogs for page conversion parts. The page size is generally 4KB. The page catalog contains 1024 catalog items, each of which has a length of 4 B. Each page catalog entry addresses a page table that contains 1024 items.

Linear address = Page Table of contents items (page directory entry) + Pages tables entry (page entry) + memory page offset address (page offset addresses)

　　

Figure Two linear address structure

Figure three page directory or page table item structure

TLB (translation look-aside buffer, convert back buffer) is a buffer memory. In 80486, the TLB saves 32 of the most recently used page conversion addresses. General instruction and data buffer memory each has a TLB.

There is only one page directory in the system, and the page directory contains 1024 double-word addresses, which can address up to 1024 page tables. Page catalogs and the length of each page table are 4KB. If 4GB of memory is paged, the system allocates 4KB of storage space for the page directory and allocates 1024*4KB=4MB storage space for 1024 page tables.

Figure Four paging mechanism

Intel microprocessor Learning Note (iv) memory paging