Lab 2 Memory Management

Common operating systems use only 0 and 3

Segment Selection Sub

DPL is the information for the segment descriptor's content segment

Interrupt and fall into the general privileged level of presentation

RPL the privilege level at which the data segment is currently being accessed for drinking
The privilege level of the CPL current code snippet

DPL Global

Access to higher-privileged segments through the gated zone

Privilege-level switching

Switching privilege levels through interrupts
Interrupt-based privilege-level conversions
Interrupt Gate

Press Stack information

Ring (0 to 3)
Privilege-level switching
Kernel state jump to user state
To construct a special stack

Stack Step1 generated in the kernel stack

Mimic the ring3 of the scene when the interrupt is generated
To toggle
Will save two more messages.
Modify the CPL Privilege level

Use the Iret command to send information to other registers with the information pop-up stack
And then it's already in the user state.

Transfer from Ring3 to RING0

Interrupt Descriptor Interrupt Service History

The information that was saved at the moment of interruption
After processing the ISR, Iret returned to Ring3.
But we can modify the stack information and leave the RING0 after the ISR is done.

The way of LAb1 Changellage

x86 Privileged Level TSS format

Task State Segment
Information that is used to store different privilege levels
We focus on stack information for different privileged levels

The CPU sets a new stack based on the information in TSS to jump to a new address based on the IDT table

The operating system should have TSS set up.

TSS Special One segment Task State Segment task status segment

There's a TSS segment

Optimization specifically has a Task Register to preserve the location of TSS,
Initialized tasks

Reference documentation for privileged-level information

Segment/Page Table

x86 Memory Management Unit MMU

Overview of the segment mechanism

x86 the hidden part of the MMU-segment selector (segment selector)

Extended Segment Selector

x86 hardward MMU-GDT tables (kernel init)

Mapping relationships in LAB1

Select the page mechanism more effective some of the main CPU are using the page mechanism

Not very understanding?

How to establish a mapping mechanism for a page

Page Mechanism overview
PDE PTE

CR3 inside is the first page of the table address

Page table entry inside the village address is the linear address

Page Table entries: page tables entries

High 20-bit is base address low 12 bits are some properties

Page table on level two

Enable page mechanism (enable paging)
The first protective mechanism of CRO is to enable
CR0 highest bit 31-bit start page mechanism

Question: Practice pmm.c inside.

x86 MMU-Establishing a mapping relationship for pages in a page table

Maps a virtual address to a physical address

x86 inside a very full page mechanism

Intel's corresponding chapters

Lab 2 Memory Management