Learning makefile for Engineering Management (1)

Introduction:

Makefile is an intelligent manager in the embedded software development environment. It can be used to construct an efficient project compilation system for us when the number of files reaches dozens or more, this significantly improves the development efficiency and subsequent update and maintenance of the project, and also enhances the code reuse rate.

Learning makefile first defines three important concepts

1. Target: the target file generated after running make.

2. Dependency: Specify the dependency between the target file and other files and intermediate target files. The depended target is also called the prerequisite for the dependency target (prerequisite ).

3. Command: tells makefile how to generate a target.

Before writing a MAKEFILE file, you must first familiarize yourself with the dependencies between the files. You can use UML to build a "dependency tree" and then use variables and functions in the makefile to express the dependency tree according to the rules.

Today I will learn about the frequently used variables:

. Phony: XXX indicates a pseudo-target, which is generally named "clean". Its main function is to avoid duplicate names of file names and "clean" in the file list, resulting in the failure to make files again.

Automatic variables:

[Email protected]: used to indicate the target in a rule. If a rule has multiple targets, [email protected] indicates any target that causes rule commands to be run.

$ ^: Indicates all the prerequisites in the rule.

$ <: The first prerequisite in the rule.

Special variables:

Make -- indicates the name of the Command currently processing makefile.

Makecmdgoals -- indicates the target name of the current build.

Note: You can specify multiple targets at the same time when running make. When make gets multiple targets, it will build the targets one by one from left to right.

Variable category and Value assignment:

There are two types of variables:

1. Recursive extension variable -- a variable defined by "=" is called recursively expanded Varible. Reference to this variable is recursive.

2. Simple extension variable-the variable defined with ": =" is called simple expanded Varible. make only one extension of the variable.

Conditional assignment and append assignment can also be implemented in makefile.

Conditional assignment "? = ": If the variable is not defined, the value on the right of the equal sign is assigned to the variable. If the variable has been defined, the original value of the variable is not changed;

Append value "+ =": Example

.PHONY:cleanobjects = main.o fun1.oobjects += fun2.o<pre name="code" class="cpp">clean:    rm objects