Make and Makefile Notes

0.make, what is makefile?

Makefile defines a series of rules to define which parts are compiled first, which are compiled after, and after the makefile is written, only one make command can get the whole project automatically compiled, so simply say,make& Makefile automates the compilation of large projects.

What's in 1.makefile?

A simple example of a makefile:

 1  TARGET:MAIN.O test.o  2  CC -o target main.o teat.o  3  main.o:main.c x.h  4  CC -5  test.o:test.c y.h  CC -c test.c  clean:  8  rm  target MAIN.O test.o 

As you can see, the makefile consists of two parts: #1文件依赖关系和 # # generates the required commands. Where clean is a pseudo-target file, available ". Phony:clean "noted in front of it. Execute the make command to compile, and do clean to delete all target files.

How does 2.make work?

0) make will find a file named "Makefile" or "makefile" in the current directory;

1) If the makefile file is found, then find the first target file and use it as the final target file;

2) If the target file relies on a later. o file update, executing the command defined later generates the target file;

3) an. o file also relies on several source files and header files, which generate. o Files according to the command.

Depending on the make, makes will go through the dependencies of the file layer by layer until the first target file is successfully compiled. The entire process is similar to the operation of a stack in a data structure.

3. Pay particular attention to variable assignments in--makefile:

"=" is the most basic assignment, makefile will expand the entire makefile, then determine the value of the variable.

": =" overrides the current value, depending on the current assignment, rather than the final assignment (better judgment).

"? =" is the value that is assigned to an equal value if it has not been assigned.

"+ =" is the value after adding an equal sign.

4. You can use variables to reduce duplication and simplify makefile using Makefile's automatic derivation, for example:

1 #Makefile 2 OBJECTS:MAIN.O TEST.O 3 target:$ (objects) 4     cc -o target $ (objects)5main.o:x.h       #这就用到了自动推导.  6test.o:y.h7. Phony:clean   #说明clean是一个伪目标文件.  8clean:9     RM target $ (objects)

Because this compilation is simpler, the advantages may not be obvious, and for large projects, the use of variables and automatic derivation can make makefile much easier. This part is actually very rich, the first suspense to this.

5. Small bet:

0) The makefile command must start with the [tab] key.

1) If you specify a specific makefile, you can use the "-F" and "--file" parameters.

2) include, the included file will be placed in the current file containing the location, such as:

Include Foo.  Make

Note that you cannot start with the [tab] key.
A simple record of your own notes, for errors and omissions, please enlighten me. For more content on make and makefile, it is recommended that Chenhao "write Makefile with Me".

Make and Makefile Notes