Makefile concise tutorial

Linux project manager make is similar to the "Project" in Windows VC. It is an "automatic compilation manager ", the system can automatically discover updated files based on the file timestamp to reduce the compilation workload. By reading the content of the MAKEFILE file to execute a large amount of compilation work, you only need to write a simple compilation statement. It improves the efficiency of the actual project, and is used in almost all program programming in Linux.

Before writing makefile, let's first take a look at the process of making:

1) read all makefile files;

2) If the makefile contains other makefile files by using include, the MAKEFILE file is read;

3) initialize the variables in the file;

4) push to obscure rules and analyze all rules;

5) create dependency chains for all target files;

6) determine the targets to be regenerated Based on the dependency relationship;

7) run the generated command.

If the defined variable is used, make adopts the procrastination strategy. If the variable appears in the dependency relationship's forehead rule, only when this dependency is determined to be used, variable is expanded internally.

                                                                                                                                                                                                                                                                                                                        

Compiling makefile

The first target in makefile will be used as its default target.

The writing format of the target, dependency, and command is

Targets: prerequisitestab command # This method is mostly used. Use the tab key to align the command.

Or

targets:prerequisites ; commandcommand

Targets without dependent files are called "pseudo targets ". It is just a tag, not a file. Make cannot generate its dependency and decide whether to execute it. Therefore, we can only explicitly specify this "target" for it to take effect-that is, we can execute it through the call shown by make + pseudo target name.

To avoid duplicate names of pseudo targets and files, you can use the special mark ". Phony" to specify a pseudo target. Whether or not this file exists, this target is a pseudo target.

. Phony: cleanclean: Rm-f *. O // no matter whether the clean file exists or not, clean is a pseudo target.

Of course, "pseudo targets" can also have dependent files. pseudo targets can also be used as "Default targets", as long as they are placed in the first. For example, if your makefile needs to generate several executable files in one breath, but you just want to simply knock a make file and write all the target files in a makefile, then you can use the "pseudo-target" feature:

all : prog1 prog2 prog3.PHONY : allprog1 : prog1.o        cc -o prog1 prog1.oprog2 : prog2.o        cc -o prog2 prog2.oprog3 : prog3.o        cc -o prog3 prog3.o 

Now, let's take the source file in the data structure C language implementation-sequential linear table sqlist as an example, first give its makefiel file. Four source files: Declaration. H, function. H, function. C, Main. c

main:main.o function.ogcc -o main main.o function.omain.o:main.c function.h declaration.hgcc -c main.cfunction.o:function.c function.h declaration.hgcc -c function.c.PHONY:cleanclean:rm *.o

This is a conventional method, and we will further optimize it.

Use Variables

Variables in makefile include User-Defined variables, pre-defined variables, automatic variables, and environment variables. The predefined variables and automatic variables are both default values, but can also be modified. Common predefined variables in makefile are as follows:

The name of the CC--C compiler, the default is the name of the cccpp -- C compiler, the default is the name of the $ (CC)-ECXX--C ++ compiler, default is g ++ Rm -- name of the file delimiters, default is RM-F CFLAGS--C compiler option no default

// Assign the initial value when declaring the variable. "$" Is added before the variable name, and "()" or "{}" is used to enclose the variable name. "$" indicates the real "$" symbol.

// If the rule command contains shell variables, reference the "$ Temp" format of shell.

Use automatic boot

Let the makefile be automatically deduced. As long as you see the. o file, it will automatically add the corresponding. c file to the dependent file, and GCC-C *. C will also be deduced. Simplified as follows

CC=gccOBJ=main.o function.oRM=rm -fmake:$(OBJ)$(CC) -o main $(OBJ)main.o:declaration.h function.hfunction.o:function.h declaration.h.PHONY:cleanclean:$(RM) $(OBJ)

Use automatic Variables

<Span style = "color: #333333;"> [email protected]: target file $ ^: All dependent files $ <: first dependent file </span>

Use default rules

. C. O: gcc-C $ <this rule indicates that all. O files are dependent on the corresponding. c files.

Use Functions

CC=gccRM=rm -fCFLAGS=-Wall -cSRCS=$(wildcard *.c)OBJS=$(patsubst %c,%o,$(SRCS))TARGET=main.PHONY:all cleanall:$(TARGET)$(TARGET):$(OBJS)$(CC) -o [email protected] $^%.o:%.c$(CC) $(CFLAGS) -o [email protected] $<clean:$(RM) *.o $(TARGET)

The wildcard and patsubst functions are used to expand and replace wildcards. SRCS = $ (wildcrad *. c) is used to compile all. c files in the current directory. $ (Patsubst %. C, %. O, $ (SRCS) replace all the variable Suffixes in $ (SRCS) with. O.

                                                                                                                                                                                                                                                                                                                   

SpecifyMakefile

The default makefile search rule of GNU make is to find three files in the current directory in sequence: "gnumakefile", "makefile", and "makefile ". These three files are searched in order. Once found, the files are read and executed.

You can also define the name of the MAKEFILE file. If the name of a makefile is mfile, run the following command:

make -f mfile/make --file mfile

Makefile concise tutorial